B. Del Signore

A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition

Qicheng Yu, B.W. Garlepp, M.H. Perrott, 2006, IEEE Journal of Solid-State Circuits.