Haidar Harmanani

An improved method for RTL synthesis with testability tradeoffs

Haidar Harmanani, Christos A. Papachristou, 1993, ICCAD.

A data path synthesis method for self-testable designs

Haidar Harmanani, Christos A. Papachristou, Scott Chiu, 1991, 28th ACM/IEEE Design Automation Conference.

A hybrid distributed test generation method using deterministic and genetic algorithms

Haidar Harmanani, Bassem Karablieh, 2005, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05).

A method for efficient NoC test scheduling using deterministic routing

Haidar Harmanani, Rana Farah, 2010, 23rd IEEE International SOC Conference.

An Approach for Redesigning in Data Path Synthesis

Haidar Harmanani, Christos A. Papachristou, Mehrdad Nourani, 1993, 30th ACM/IEEE Design Automation Conference.

Test bus assignment, sizing, and partitioning for system-on-chip

Haidar Harmanani, Rachel Sawan, 2007, Canadian Journal of Electrical and Computer Engineering.

A Genetic Algorithm for the Maximum Clique Problem

Haidar Harmanani, Rebecca Moussa, Romario Akiki, 2019, 16th International Conference on Information Technology-New Generations (ITNG 2019).

SYNTEST: a method for high-level SYNthesis with self-TESTability

Haidar Harmanani, Christos A. Papachristou, Scott Chiu, 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.