T. Chou

Integration Design of Chip and Package for Cost-Effective High-Speed Applications

Nansen Chen, Hongchin Lin, Nan-Cheng Chen, 2005, 2005 IEEE Conference on Electron Devices and Solid-State Circuits.

Flip chip power cycling system development and lead free bump power cycling reliability

K. Wu, M. J. Lii, L. Lin, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

A high performance 0.13 /spl mu/m SOI CMOS technology with a 70 nm silicon film and with a second generation low-k Cu BEOL

G. Biery, S. Narasimha, J. Adkisson, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).