Basireddy Karunakar Reddy

发表

A Novel Physical Synthesis Methodology in the VLSI Design Automation by Introducing Dynamic Library Concept

Jimson Mathew, Rishad A. Shafik, Amit Acharyya, 2013, 2013 International Symposium on Electronic System Design.

Online concurrent workload classification for multi-core energy management

Geoff V. Merrett, Bashir M. Al-Hashimi, Amit Kumar Singh, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Novel and Unified Digital IC Design and Automation Methodology with Reduced NRE Cost and Time-to-Market

Jimson Mathew, Rishad A. Shafik, Amit Acharyya, 2013, 2013 International Symposium on Electronic System Design.

Active Cooling Technique for Efficient Heat Mitigation in 3D-ICs

Basireddy Karunakar Reddy, Shiv Govind Singh, Pramod Kaddi, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

Workload-Aware Runtime Energy Management for HPC Systems

Geoff V. Merrett, Bashir M. Al-Hashimi, Eduardo Wächter, 2018, 2018 International Conference on High Performance Computing & Simulation (HPCS).

Energy-Efficient Run-Time Mapping and Thread Partitioning of Concurrent OpenCL Applications on CPU-GPU MPSoCs

Geoff V. Merrett, Bashir M. Al-Hashimi, Amit Kumar Singh, 2017, ACM Trans. Embed. Comput. Syst..

EdgeCoolingMode: An Agent Based Thermal Management Mechanism for DVFS Enabled Heterogeneous MPSoCs

Xiaohang Wang, Amit Kumar Singh, Klaus D. McDonald-Maier, 2019, 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID).

Novel ASIC Design Flow Using Dynamic Libraries for Reducing Design Time

Amit Acharyya, Srinivas Sabbavarapu, Basireddy Karunakar Reddy, 2018, J. Low Power Electron..

A New Dynamic Library Based IC Design Automation Methodology Using Functional Symmetry with NPN Class Representation Approach to Reduce NRE Costs and Time-to-Market

Amit Acharyya, Srinivas Sabbavarapu, Basireddy Karunakar Reddy, 2014, 2014 Fifth International Symposium on Electronic System Design.

Inter-Cluster Thread-to-Core Mapping and DVFS on Heterogeneous Multi-Cores

Geoff V. Merrett, Bashir M. Al-Hashimi, Amit Kumar Singh, 2018, IEEE Transactions on Multi-Scale Computing Systems.

Learning-Based Run-Time Power and Energy Management of Multi/Many-Core Systems: Current and Future Trends

Geoff V. Merrett, Bashir M. Al-Hashimi, Amit Kumar Singh, 2017, J. Low Power Electron..

Cut-less Technology Mapping Using Shannon Factor Graph with on-the-fly Size Reduction

Amit Acharyya, Srinivas Sabbavarapu, Basireddy Karunakar Reddy, 2018, J. Low Power Electron..

Improved Wire Length-Driven Placement Technique for Minimizing Wire Length, Area and Timing

S. Saqib Khursheed, Amit Acharyya, Srinivas Sabbavarapu, 2017, J. Low Power Electron..

A new VLSI IC design automation methodology with reduced NRE costs and time-to-market using the NPN class Representation and functional symmetry

Amit Acharyya, Srinivas Sabbavarapu, Basireddy Karunakar Reddy, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

A Novel Integrated Circuit Design Methodology Using Dynamic Library Concept with Reduced Non-Recurring Engineering Cost and Time-to-Market

Jimson Mathew, Amit Acharyya, Srinivas Sabbavarapu, 2014, J. Low Power Electron..

Empirical CPU power modelling and estimation in the gem5 simulator

Geoff V. Merrett, Bashir M. Al-Hashimi, Matthew J. Walker, 2017, 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Effect of Constant One and Zero, Shared and Non-decomposed Nodes on Runtime and Graph Size of the Shannon Factor Graph (SFG)

Amit Acharyya, Srinivas Sabbavarapu, Basireddy Karunakar Reddy, 2014, 2014 Fifth International Symposium on Electronic System Design.