Nagarajan Ranganathan

发表

A VLSI hardware accelerator for dynamic time warping

Ravi Sankar, V. K. Sundaresan, S. Nichani, 1992, Proceedings., 11th IAPR International Conference on Pattern Recognition. Vol. IV. Conference D: Architectures for Vision and Pattern Recognition,.

Journal of Homeland Security and Emergency Management An Automated Decision Support System Based on Game Theoretic Optimization for Emergency Management in Urban Environments

Ashok K. Murugavel, Nagarajan Ranganathan, Upavan Gupta, 2011 .

Improving bandwidth of communication controllers

Mostafa A. Bassiouni, Amar Mukherjee, Nagarajan Ranganathan, 1988, IEEE International Conference on Communications, - Spanning the Universe..

A new design of the reversible subtractor circuit

Himanshu Thapliyal, Nagarajan Ranganathan, H. Thapliyal, 2011, 2011 11th IEEE International Conference on Nanotechnology.

Efficient transportation of vbr video traffic in atm networks

Ravi Sankar, Nagarajan Ranganathan, G. Chiruvolu, 1998 .

Design of A ternary barrel shifter using multiple-valued reversible logic

Himanshu Thapliyal, Nagarajan Ranganathan, Saurabh Kotiyal, 2010, 10th IEEE International Conference on Nanotechnology.

Adaptive and pipelined VLSI designs for tree-based codes

Mostafa A. Bassiouni, Amar Mukherjee, Nagarajan Ranganathan, 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Fast spatiotemporal filters

Rajiv Mehrotra, Nagarajan Ranganathan, K. R. Namaduri, 1990, [1990] Proceedings. 10th International Conference on Pattern Recognition.

Vlsi Algorithms and Architectures

Nagarajan Ranganathan, 1993 .

A scale-space chip

Mubarak Shah, Nagarajan Ranganathan, 1988, [1988 Proceedings] 9th International Conference on Pattern Recognition.

Issues and approaches towards VBR video traffic management in ATM networks

Ravi Sankar, Nagarajan Ranganathan, G. Chiruvolu, 1998, Proceedings IEEE Southeastcon '98 'Engineering for a New Era'.

Structure de circuit vlsi pour la mise en application du standard de compression d'images jpeg

Nagarajan Ranganathan, Mario Kovac, 1995 .

A suggestion for performance improvement in a relational database machine

Nagarajan Ranganathan, H. N. Srinidhi, 1991 .

~go~it~~§ For Tree Pattern

Abdel Ejnioui, Nagarajan Ranganathan, 1995 .

Design of a reversible single precision floating point multiplier based on operand decomposition

Himanshu Thapliyal, Nagarajan Ranganathan, Michael Nachtigal, 2010, 10th IEEE International Conference on Nanotechnology.

High-speed VLSI designs for Lempel-Ziv-based data compression

Nagarajan Ranganathan, S. Henriques, N. Ranganathan, 1993 .

A System Architecture for the Detection of Insider Attacks in Big Data Systems

Santosh Aditham, Nagarajan Ranganathan, 2018, IEEE Transactions on Dependable and Secure Computing.

Réalisation d'un caisson hermétique pour essais dynamiques

Nagarajan Ranganathan, Johann Petit, A. Nadeau, 1980 .

Design of static and dynamic RAM arrays using a novel reversible logic gate and decoder

Matthew Morrison, Nagarajan Ranganathan, Matthew Lewandowski, 2011, 2011 11th IEEE International Conference on Nanotechnology.

Design of a systolic VLSI chip for computing scale space

Nagarajan Ranganathan, Sanjay Nichani, 1992, Defense, Security, and Sensing.

Design of a Moore finite state machine using a novel reversible logic gate, decoder and synchronous up-counter

Matthew Morrison, Nagarajan Ranganathan, N. Ranganathan, 2011, 2011 11th IEEE International Conference on Nanotechnology.

A systolic architecture for LZ based decompression

Nagarajan Ranganathan, S. Henriques, 1991, [1991] Proceedings. Data Compression Conference.

FPGA Synthesis and CAD for Reconfigurable Systems

Luca Benini, Stephen A. Edwards, Yunheung Paek, 2009 .

ANovelApproach forVariation Aware PowerMinimization during GateSizing

V. Mahalingam, Nagarajan Ranganathan, Justin E. Harlow, 2006 .

Utilitarian Approaches for Multi-Metric Optimization in VLSI Circuit Design and Spatial Clustering

Nagarajan Ranganathan, Upavan Gupta, Upavan Gupta, 2008 .

ACE: a VLSI chip for Galois field GF(2/sup m/) based exponentiation

Nagarajan Ranganathan, M. Kovac, 1996 .

A VLSI architecture for hierarchical scene matching

Nagarajan Ranganathan, R. Venkatesan, R. Sastry, 1992, Proceedings., 11th IAPR International Conference on Pattern Recognition. Vol. IV. Conference D: Architectures for Vision and Pattern Recognition,.

JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard

Nagarajan Ranganathan, M. Kovac, N. Ranganathan, 1995, Proc. IEEE.

A new CRL gate as super class of Fredkin gate to design reversible quantum circuits

Himanshu Thapliyal, Nagarajan Ranganathan, Apeksha Bhatt, 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

Design of a reversible bidirectional barrel shifter

Himanshu Thapliyal, Nagarajan Ranganathan, Saurabh Kotiyal, 2011, 2011 11th IEEE International Conference on Nanotechnology.

Hardware Implementation of Data Compression

Sanjukta Bhanja, Nagarajan Ranganathan, 2003 .

A VLSI architecture for difference picture-based dynamic scene analysis

Rajiv Mehrotra, Nagarajan Ranganathan, 1990, [1990] Proceedings. 10th International Conference on Pattern Recognition.

SIBA: a VLSI systolic array chip for image processing

Nagarajan Ranganathan, M. Patel, P. A. McCabe, 1992, Proceedings., 11th IAPR International Conference on Pattern Recognition. Vol. IV. Conference D: Architectures for Vision and Pattern Recognition,.

Design of a reversible floating-point adder architecture

Himanshu Thapliyal, Nagarajan Ranganathan, Michael Nachtigal, 2011, 2011 11th IEEE International Conference on Nanotechnology.

SYSTOLIC ARCHITECTURES FOR PARTIAL POLYGON RECOGNITION

Horst Bunke, Nagarajan Ranganathan, R. Sastry, 1993 .

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Radu Marculescu, Majid Sarrafzadeh, Vishwani D. Agrawal, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design and analysis of a novel reversible encoder/decoder

Nagarajan Ranganathan, Michael Nachtigal, 2011, 2011 11th IEEE International Conference on Nanotechnology.

An architecture to implement multiresolution

Nagarajan Ranganathan, Kamesh Namuduri, R. Mehrotra, 1991, [Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing.

A scene-based generalized Markov chain model for VBR video traffic

Tapas K. Das, Ravi Sankar, Nagarajan Ranganathan, 1998, ICC '98. 1998 IEEE International Conference on Communications. Conference Record. Affiliated with SUPERCOMM'98 (Cat. No.98CH36220).

Efficient VLSI designs for data transformation of tree-based codes

Mostafa A. Bassiouni, Amar Mukherjee, Nagarajan Ranganathan, 1991 .

Another Step in the Right Direction for TVLSI

Nagarajan Ranganathan, N. Ranganathan, 2004 .

New methods for dynamic power estimation and optimization in vlsi circuits

Ashok K. Murugavel, Nagarajan Ranganathan, 2003 .

VLSI algorithms for data compression

Mostafa A. Bassiouni, Amar Mukherjee, Nagarajan Ranganathan, 1991 .

Design of a novel reversible ALU using an enhanced carry look- ahead adder

Matthew Morrison, Nagarajan Ranganathan, Richard Meana, 2011, 2011 11th IEEE International Conference on Nanotechnology.

A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing

Nagarajan Ranganathan, Narender Hanchate, 2004 .