Sudhakar M. Reddy

发表

Design and analysis of fault-tolerant multistage interconnection networks with low link complexity

V. P. Kumar, Sudhakar M. Reddy, 1985, ISCA 1985.

An Investigation into Redundancy and Testability of Combinational Logic Networks.

John P. Robinson, Sudhakar M. Reddy, Ramaswami Dandapani, 1970 .

ScanDesign UsingStandard Flip-Flops

R. Dandapani, Sudhakar M. Reddy, 1987 .

An improved source design for scan BIST

Irith Pomeranz, Sudhakar M. Reddy, Wei Li, 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

Combinationally irredundant ISCAS-89 benchmark circuits

Kozo Kinoshita, I. Pomeranz, Sudhakar M. Reddy, 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

An Improved Markov Source Design for Scan BIST

Irith Pomeranz, Sudhakar M. Reddy, Wei Li, 2003 .

Fault modeling and test generation

Vishwani D. Agrawal, Sudhakar M. Reddy, 1991 .

On timing faults in digital logic circuits

Sudhakar M. Reddy, 1993 .

Error-Control Teckniques rorLogic Processors

Sudhakar M. Reddy, 1972 .

FAULT-DIAGNOSIS IN FULLY DISTRIBUTED SYSTEMS

Sudhakar M. Reddy, Jon G. Kuhl, 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'..

Design Techniques for Synthesis of Fault-Tolerant Asynchronous Networks.

Dhiraj K. Pradhan, Sudhakar M. Reddy, 1972 .

Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin, 1999 .

Local Transformations and Robust Dependent Path Delay

Bernd Becker, Uwe Sparmann, Sudhakar M. Reddy, 1996 .

Sudhakar M. Reddy, Sitaram Yadavalli, 1996 .