K. K. Mahapatra

发表

An study of removal of subjective redundancy in JPEG for low cost, low power, computation efficient circuit design and high compression image

Vijay Kumar Sharma, U. C. Pati, K. K. Mahapatra, 2010, 2010 International Conference on Power, Control and Embedded Systems.

Low latency VLSI architecture of S-box for AES encryption

Saurabh Kumar, K. K. Mahapatra, V.K. Sharma, 2013, 2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT).

A low-power circuit technique for domino CMOS logic

K. K. Mahapatra, P. Meher, K. Mahapatra, 2013, 2013 International Conference on Intelligent Systems and Signal Processing (ISSP).

On-chip comparison based secure output response compactor for scan-based attack resistance

Sauvagya Ranjan Sahoo, K. K. Mahapatra, Sudeendra Kumar K, 2015, 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA).

A high speed low power encoder for a 5 bit flash ADC

K. K. Mahapatra, G. T. Varghese, 2012, 2012 International Conference on Green Technologies (ICGT).

Improved techniques for high performance noise-tolerant domino CMOS logic circuits

K. K. Mahapatra, D. S. V. S. Sarma, K. Mahapatra, 2012, 2012 Students Conference on Engineering and Systems.

A Novel PUF Based SST to Prevent Distribution of Rejected ICs from Untrusted Assembly

G. Hanumantha Rao, K. K. Mahapatra, K. Sudeendra Kumar, 2015, 2015 IEEE International Symposium on Nanoelectronic and Information Systems.

FPGA implementation of digital controller for active power line conditioner using SRF theory

K. K. Mahapatra, Prabhat Kumar Barik, Saswat Kumar Ram, 2011, 2011 10th International Conference on Environment and Electrical Engineering.

Fuzzy logic based integrated control of Anti-lock Brake System and Collision Avoidance System using CAN for electric vehicles

K. K. Mahapatra, K. Sudeendra kumar, Leslin Verghese, 2009, 2009 IEEE International Conference on Industrial Technology.

EFFICIENT MULTIPLIER- LESS VLSI ARCHITECTURES FOR FOLDED PIPELINED COMPLEX FFT CORE 2013

K. K. Mahapatra, 2013 .

Real-Time Implementation of Fast Fourier Transform (FFT) and Finding the Power Spectrum Using LabVIEW and CompactRIO

K. K. Mahapatra, A. D. Das, 2013, 2013 International Conference on Communication Systems and Network Technologies.

Class-C power amplifier design for GSM application

K. K. Mahapatra, L. Samal, K. Raghuramaiah, 2012, 2012 International Conference on Computing, Communication and Applications.

Design of low power and high speed ripple carry adder using modified feedthrough logic

K. K. Mahapatra, S. R. Sahoo, 2012, 2012 International Conference on Communications, Devices and Intelligent Systems (CODIS).

Modified circuit design technique for feedthrough logic

K. K. Mahapatra, S. R. Sahoo, 2012, 2012 NATIONAL CONFERENCE ON COMPUTING AND COMMUNICATION SYSTEMS.

An Improved VLSI Architecture of S-box for AES Encryption

S. Kumar, K. K. Mahapatra, V. K. Sharma, 2013, 2013 International Conference on Communication Systems and Network Technologies.

Ultra low-power and noise tolerant CMOS dynamic circuit technique

Preetisudha Meher, K. K. Mahapatra, 2011, TENCON 2011 - 2011 IEEE Region 10 Conference.

An Efficient Distributed Arithmetic Based VLSI Architecture for DCT

Vijay Kumar Sharma, Umesh C. Pati, K. K. Mahapatra, 2011, 2011 International Conference on Devices and Communications (ICDeCom).

Design and error analysis of a scale free CORDIC unit with corrected scale factor

N. Prasad, K. K. Mahapatra, A. K. Swain, 2012, 2012 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics.

Realization of reconfigurable FLC on ADSP-BF537 processor

S. K. Patra, K. K. Mahapatra, J. Govindarajan, 2013, 2013 Fourth International Conference on Computing, Communications and Networking Technologies (ICCCNT).

Robust facial expression recognition using Gabor feature and Bayesian discriminating classifier

K. K. Mahapatra, Yamini Piparsaniyan, Vijay K. Sharma, 2014, 2014 International Conference on Communication and Signal Processing.

A high speed encoder for a 5GS/s 5 bit flash ADC

K. K. Mahapatra, G. T. Varghese, 2012, 2012 Third International Conference on Computing, Communication and Networking Technologies (ICCCNT'12).

Performance analysis of modified feedthrough logic for low power and high speed

K. K. Mahapatra, S. R. Sahoo, S. Sahoo, 2012, IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012).

FPGA implementation of pipelined CORDIC based quadrature direct digital synthesizer with improved SFDR

Ayas Kanta Swain, K. K. Mahapatra, N Prasad, 2013, 2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT).

Simplified model for control design of STATCOM using three-level inverter

Arindam Ghosh, K. K. Mahapatra, S. R. Doradla, 1998, Proceedings of IEEE TENCON '98. IEEE Region 10 International Conference on Global Connectivity in Energy, Computer, Communication and Control (Cat. No.98CH36229).

An ultra low power encoder for 5 bit flash ADC

K. K. Mahapatra, G. T. Varghese, Y. Lavania, 2013, 2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT).

A high-performance circuit technique for CMOS dynamic logic

Preetisudha Meher, K. K. Mahapatra, 2011, 2011 IEEE Recent Advances in Intelligent Computational Systems.

Design and analysis of five port router for network on chip

K. K. Mahapatra, A. K. Swain, S. Swapna, 2012, 2012 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics.

A novel control circuit for aircraft power supply using soft-switched inverter

K. K. Mahapatra, S. Kumar Pattanaik, 2009, 2009 IEEE International Conference on Industrial Technology.

Hardware Trojans: A State of the Art

K. K. Mahapatra, K Sudeendra Kumar, 2015 .

2-D Separable discrete Hartley transform architecture for efficient FPGA resource

Richa Agrawal, Vijay Kumar Sharma, U. C. Pati, 2010, 2010 International Conference on Computer and Communication Technology (ICCCT).

A technique to increase noise-tolerance in dynamic digital circuits

K. K. Mahapatra, P. Meher, 2012, 2012 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics.

Power efficient design of a novel SRAM cell with higher write ability

K. K. Mahapatra, D. P. Acharya, Debasish Nayak, 2015, 2015 Annual IEEE India Conference (INDICON).