Régis Leveugle

发表

The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis

Norbert Wehn, Israel Koren, Zahava Koren, 1994, IEEE Trans. Computers.

Complementary Formal Approaches for Dependability Analysis

Emmanuelle Encrenaz-Tiphène, Souheib Baarir, Régis Leveugle, 2009, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Using run-time reconfiguration for fault injection in hardware prototypes

Régis Leveugle, Lörinc Antoni, Béla Fehér, 2000, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model

Giorgio Di Natale, Régis Leveugle, Jean-Max Dutertre, 2018, 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC).

Tutorial 1: “New approaches towards early dependability evaluation of digital integrated systems”

Régis Leveugle, 2016, 2016 11th International Design & Test Symposium (IDT).

Laser-induced fault effects in security-dedicated circuits

Giorgio Di Natale, Régis Leveugle, Jean-Max Dutertre, 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

Usefulness and effectiveness of HW and SW protection mechanisms in a processor-based system

Régis Leveugle, Philippe Roche, Michele Portolan, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA

Frédéric Valette, Régis Leveugle, Jessy Clédière, 2009, 2009 27th IEEE VLSI Test Symposium.

Design of defect-tolerant scan chains for MCMs with an active substrate

Régis Leveugle, Gabriele Saucier, P. Brahic, 1995, Proceedings of International Workshop on Defect and Fault Tolerance in VLSI.

Multi-level fault injection experiments based on VHDL descriptions: a case study

Régis Leveugle, K. Hadjiat, 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).

Special section on defect and fault tolerance in VLSI systems

Glenn H. Chapman, Régis Leveugle, 2003, Microelectron. J..

Configuration errors analysis in SRAM-based FPGAs: Software tool and practical results

Régis Leveugle, Vincent Pouget, Vincent Maingot, 2007, Microelectron. Reliab..

Optimized synthesis of dedicated controllers with concurrent checking capabilities

Régis Leveugle, Gabriele Saucier, R. Leveugle, 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

Clocking scheme selection for circuits made up of a controller and a datapath

Régis Leveugle, C. Safina, 1992, Synthesis for Control Dominated Circuits.

Dependability issues in SRAM-based FPGA design

Régis Leveugle, 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.

Criticality evaluation of embedded software running on a pipelined microprocessor and impact of compilation options

Régis Leveugle, Michele Portolan, Salma Bergaoui, 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Design of microprocessors with built-in on-line test

Régis Leveugle, T. Michel, Gabriele Saucier, 1990, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium.

Automatic and optimized synthesis of dataparts with fault detection or tolerance capabilities

Régis Leveugle, Lionel Revéret, H. Chauvet, 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Laser-induced fault effects in security-dedicated circuits

Giorgio Di Natale, Régis Leveugle, Jean-Max Dutertre, 2014, VLSI-SoC.

A new methodology for accurate predictive robustness analysis of designs implemented in SRAM-based FPGAs

Régis Leveugle, Mohamed Ben Jrad, 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

Forecasting the Effects of Electromagnetic Fault Injections on Embedded Cryptosystems

Régis Leveugle, Paolo Maistri, Diego Alberto, 2013, Inf. Secur. J. A Glob. Perspect..

Asynchronous circuits sensitivity to fault injection

Régis Leveugle, Marc Renaudin, Yannick Monnet, 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

High level modifications of VHDL descriptions for on-line test or fault tolerance

Régis Leveugle, R. Cercueil, 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

ROM-based synthesis of fault-tolerant controllers

Régis Leveugle, X. Wendling, Raphaël Rochet, 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis

Régis Leveugle, Philippe Roche, Pierre Vanhauwaert, 2006, 2006 IFIP International Conference on Very Large Scale Integration.

Influence of error correlations on the signature analysis aliasing

Régis Leveugle, Gabriele Saucier, X. Delord, 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

Software BIST capabilities of a symmetric cipher

Régis Leveugle, Paolo Maistri, Cyril Excoffon, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

Hardening techniques against transient faults for asynchronous circuits

Régis Leveugle, Marc Renaudin, Yannick Monnet, 2005, 11th IEEE International On-Line Testing Symposium.

Optimized Synthesis of Concurrently Checked Controllers

Régis Leveugle, Gabriele Saucier, 1990, IEEE Trans. Computers.

A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks

Régis Leveugle, Vincent Beroulle, Paolo Maistri, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A new approach for early dependability evaluation based on formal property checking and controlled mutations

Régis Leveugle, R. Leveugle, 2005, 11th IEEE International On-Line Testing Symposium.

Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments

Régis Leveugle, K. Hadjiat, 2003, J. Electron. Test..

Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic

Régis Leveugle, Marc Renaudin, Yannick Monnet, 2006, IEEE Transactions on Computers.

On the development of a new countermeasure based on a laser attack RTL fault model

Régis Leveugle, Vincent Beroulle, Paolo Maistri, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Pattern-based injections in processors implemented on SRAM-based FPGAs

Régis Leveugle, Mohamed Ben Jrad, 2012, 2012 13th Latin American Test Workshop (LATW).

On fault injections for early security evaluation vs. laser-based attacks

Régis Leveugle, Vincent Beroulle, Paolo Maistri, 2016, 2016 1st IEEE International Verification and Security Workshop (IVSW).

Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections

Régis Leveugle, Paolo Maistri, Pierre Vanhauwaert, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

ACL2 for the verification of fault-tolerance properties: first results

Laurence Pierre, Régis Leveugle, Renaud Clavel, 2009, ACL2 '09.

Alternative approaches to fault detection in FSMs

Régis Leveugle, Gabriele Saucier, Raphaël Rochet, 1994, IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

Chip level security: Why ? How ?

Régis Leveugle, 2008, ICECS.

Test of single fault tolerant controllers in VLSI circuits

Régis Leveugle, 1993, VLSI.

Evaluating a low cost robustness improvement in SRAM-based FPGAs

Régis Leveugle, Mohamed Ben Jrad, 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).

A low-cost hardware approach to dependability validation of IPs

Régis Leveugle, 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

On-Line Testing for Secure Implementations: Design and Validation

Yervant Zorian, Jean-Pierre Seifert, Régis Leveugle, 2005, IOLTS.

On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors

Régis Leveugle, Michele Portolan, 2005, IOLTS.

IDSM: An improved disjoint signature monitoring scheme for processor behavioral checking

Régis Leveugle, Salma Bergaoui, Pierre Vanhauwaert, 2014, 2014 15th Latin American Test Workshop - LATW.

Statistical fault injection: Quantified error and confidence

Régis Leveugle, Paolo Maistri, Pierre Vanhauwaert, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Double-Data-Rate Computation as a Countermeasure against Fault Analysis

Régis Leveugle, Paolo Maistri, R. Leveugle, 2008, IEEE Transactions on Computers.

System-level dependability analysis with RT-level fault injection accuracy

Régis Leveugle, D. Cimonnet, Abdelaziz Ammari, 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

Operating System Function Reuse to Achieve Low-Cost Fault Tolerance

Régis Leveugle, Michele Portolan, 2004, IOLTS.

An Elliptic Curve Crypto-Processor Secured by Randomized Windows

Régis Leveugle, Paolo Maistri, Simon Pontie, 2014, 2014 17th Euromicro Conference on Digital System Design.

A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System

Régis Leveugle, Paolo Maistri, Lorena Anghel, 2020, 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems

Régis Leveugle, Vincent Beroulle, Lilian Bossuet, 2020, 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Taking advantage of high level functional information to refine timing analysis and timing information

Régis Leveugle, Gabriele Saucier, C. Safinia, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

Evaluation of SET and SEU effects at multiple abstraction levels

Lorena Anghel, Régis Leveugle, Pierre Vanhauwaert, 2005, 11th IEEE International On-Line Testing Symposium.

Synthesis of large controllers using ROM or PLA generators

Régis Leveugle, Gabriele Saucier, Laurent Gerbaux, 1992, Synthesis for Control Dominated Circuits.

Introduction to the special session on secure implementations

Régis Leveugle, 2005, 11th IEEE International On-Line Testing Symposium.

A synthesis tool for fault-tolerant finite state machines

Régis Leveugle, Gabriele Saucier, L. Martinez, 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.

Towards Robustness Analysis Using PVS

Laurence Pierre, Régis Leveugle, Renaud Clavel, 2011, ITP.

A flexible RNS-based large polynomial multiplier for Fully Homomorphic Encryption

Rached Tourki, Régis Leveugle, Mohsen Machhout, 2016, 2016 11th International Design & Test Symposium (IDT).

Error Detection Code Efficiency for Secure Chips

Régis Leveugle, Vincent Maingot, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

Analysis and comparison of fault tolerant FSM architecture based on SEC codes

Régis Leveugle, Gabriele Saucier, Raphaël Rochet, 1993, Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

Taking into account indirect jumps or calls in continuous control-flow checking

Régis Leveugle, Yannick Teglia, Michel Agoyan, 2016, 2016 11th International Design & Test Symposium (IDT).

Efficient synthesis of fault-tolerant controllers

Régis Leveugle, Gabriele Saucier, Raphaël Rochet, 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

Using run-time reconfiguration for fault injection applications

Régis Leveugle, Lörinc Antoni, Béla Fehér, 2003, IEEE Trans. Instrum. Meas..

Evaluation of a software-based error detection technique by RT-level fault injection

Yvon Savaria, Régis Leveugle, Bogdan Nicolescu, 2006, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06).

Asynchronous circuits transient faults sensitivity evaluation

Régis Leveugle, Marc Renaudin, Yannick Monnet, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Hierarchical Test Generation Based on Delayed Propagation

Régis Leveugle, Gabriele Saucier, Margot Karam, 1991, 1991, Proceedings. International Test Conference.

Taking advantage of ASICs to improve dependability with very low overheads /spl lsqb/PLC/spl rsqb/

Régis Leveugle, Gabriele Saucier, T. Michel, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

CNTFET Modeling and Reconfigurable Logic-Circuit Design

Frédéric Gaffiot, Lorena Anghel, Régis Leveugle, 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

Hardware Support for Security in the Internet of Things: From Lightweight Countermeasures to Accelerated Homomorphic Encryption

Régis Leveugle, Paolo Maistri, Asma Mkhinini, 2018, Inf..

On Deratings to Refine System-Level Failure Rate Estimations

Régis Leveugle, Christophe Smekens, Christophe Smekens, 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.

An evaluation of an AES implementation protected against EM analysis

Israel Koren, Régis Leveugle, Philippe Maurine, 2013, GLSVLSI '13.

Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA

Frédéric Valette, Régis Leveugle, Jessy Clédière, 2010, 2010 15th IEEE European Test Symposium.

HLS design of a hardware accelerator for Homomorphic Encryption

Rached Tourki, Régis Leveugle, Paolo Maistri, 2017, 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Case Study of a Fault Attack on Asynchronous DES Crypto-Processors

Christophe Clavier, Régis Leveugle, Marc Renaudin, 2006, FDTC.

Analysis of laser-induced errors: RTL fault models versus layout locality characteristics

Régis Leveugle, Vincent Beroulle, Paolo Maistri, 2016, Microprocess. Microsystems.

Experimental Evaluation of Protections Against Laser-induced Faults and Consequences on Fault Modeling

Régis Leveugle, Assia Tria, Jean-Baptiste Rigaud, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Automated design flow for no-cost configuration error detection in sram-based FPGAs

Régis Leveugle, Mohamed Ben Jrad, 2013, 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig).

Software Self-Testing of a Symmetric Cipher with Error Detection Capability

Régis Leveugle, Paolo Maistri, Cyril Excoffon, 2008, 2008 14th IEEE International On-Line Testing Symposium.

On combining fault classification and error propagation analysis in RT-Level dependability evaluation

Régis Leveugle, K. Hadjiat, Abdelaziz Ammari, 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

Experiments on multimedia support of VLSI design teaching in the MODEM project

Régis Leveugle, Alejandro Chagoya, 1999, Proceedings 1999 IEEE International Conference on Microelectronic Systems Education (MSE'99) 'Systems Education in the 21st Century' (Cat. No.99-63794).

Detailed Analysis of Compilation Options for Robust Software-based Embedded Systems

Régis Leveugle, Salma Bergaoui, A. Wecxsteen, 2013, J. Electron. Test..

Towards a Secure and Reliable System

Régis Leveugle, Michele Portolan, 2005, EUC.

Using run-time reconfiguration for fault injection in hardware prototypes

Régis Leveugle, Lörinc Antoni, Béla Fehér, 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

On the Use of Information Redundancy When Designing Secure Chips

Régis Leveugle, Vincent Maingot, 2006, 2006 IEEE Design and Diagnostics of Electronic Circuits and systems.

Evaluating application-aware soft error effects in digital circuits without fault injections or probabilistic computations

Régis Leveugle, Michele Portolan, K. Chibani, 2016, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS).

Early Robustness Evaluation of Digital Integrated Systems

Régis Leveugle, 2010, FDL.

A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection

Régis Leveugle, Paolo Maistri, Pierre Vanhauwaert, 2007, Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC 2007).

HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic

Régis Leveugle, Frédéric Rousseau, Alban Bourge, 2016, 2016 Euromicro Conference on Digital System Design (DSD).

High Level Fault Injection Method for Evaluating Critical System Parameter Ranges

Régis Leveugle, Vincent Beroulle, Lilian Bossuet, 2020, 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Logic synthesis for automatic layout

Régis Leveugle, Gabriele Saucier, Pierre Abouzeid, 1992, Proceedings Euro ASIC '92.

Impact of Software Optimization on Variable Lifetimes in a Microprocessor-Based System

Régis Leveugle, Salma Bergaoui, 2011, 2011 Sixth IEEE International Symposium on Electronic Design, Test and Application.

Dummy operations in scalar multiplication over elliptic curves: A tradeoff between security and performance

Régis Leveugle, Paolo Maistri, Simon Pontie, 2016, Microprocess. Microsystems.

On error models for RTL security evaluations

Régis Leveugle, Vincent Beroulle, Paolo Maistri, 2014, 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Validation of RTL laser fault injection model with respect to layout information

Régis Leveugle, Vincent Beroulle, Paolo Maistri, 2015, 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

Fault injection in VHDL descriptions and emulation

Régis Leveugle, 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA

Régis Leveugle, Jessy Clédière, Paolo Maistri, 2011, Journal of Cryptology.

Standard and ROM-based synthesis of FSMs with control flow checking capabilities

Régis Leveugle, X. Wendling, Raphaël Rochet, 1996, Proceedings of 14th VLSI Test Symposium.

Dependability analysis: a new application for run-time reconfiguration

Régis Leveugle, Lörinc Antoni, Béla Fehér, 2003, Proceedings International Parallel and Distributed Processing Symposium.

Automatic modifications of high level VHDL descriptions for fault detection or tolerance

Régis Leveugle, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Generation of optimized datapaths: bit-slice versus standard cells

Régis Leveugle, C. Safina, 1992, Synthesis for Control Dominated Circuits.

Polynomial multipliers for fully homomorphic encryption on FPGA

Régis Leveugle, Philippe Elbaz-Vincent, Paolo Maistri, 2015, 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

Detailed comparison of dependability analyses performed at RT and gate levels

Régis Leveugle, Massimo Violante, Matteo Sonza Reorda, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

Electromagnetic analysis and fault injection onto secure circuits

Régis Leveugle, Jean-Max Dutertre, Bruno Robisson, 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA

Frédéric Valette, Régis Leveugle, Jessy Clédière, 2008, 2008 14th IEEE International On-Line Testing Symposium.

Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor

Régis Leveugle, Michele Portolan, K. Chibani, 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

A Comprehensive Approach to a Trusted Test Infrastructure

Giorgio Di Natale, Régis Leveugle, Paolo Maistri, 2019, 2019 IEEE 4th International Verification and Security Workshop (IVSW).

Reliability of computing systems: From flip flops to variables

Giorgio Di Natale, Alberto Bosio, Régis Leveugle, 2017, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS).

Towards automated fault pruning with Petri Nets

Régis Leveugle, Paolo Maistri, 2009, 2009 15th IEEE International On-Line Testing Symposium.

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

Giorgio Di Natale, Régis Leveugle, Jean-Max Dutertre, 2018, 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).

10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard

Régis Leveugle, Paolo Maistri, 2011, 2011 14th Euromicro Conference on Digital System Design.

A new approach to control flow checking without program modification

Régis Leveugle, Gabriele Saucier, T. Michel, 1991, [1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium.

A Flexible SoPC-based Fault Injection Environment

Régis Leveugle, Philippe Roche, Pierre Vanhauwaert, 2006, 2006 IEEE Design and Diagnostics of Electronic Circuits and systems.

Optimized State Assignment of Single Fault Tolerant FSMs Based on SEC Codes

Régis Leveugle, 1993, 30th ACM/IEEE Design Automation Conference.

Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA

Frédéric Valette, Régis Leveugle, Jessy Clédière, 2010, ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors.

Early SEU fault injection in digital, analog and mixed signal circuits: a global flow

Régis Leveugle, Abdelaziz Ammari, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Detailed Analysis of Compilation Options for Robust Software-based Embedded Systems

Régis Leveugle, Salma Bergaoui, A. Wecxsteen, 2012, Journal of Electronic Testing.

Practical evaluation of fault countermeasures on asynchronous DES crypto processor

Régis Leveugle, Marc Renaudin, Pascal Moitrel, 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

Electromagnetic attacks on embedded devices: A model of probe-circuit power coupling

Régis Leveugle, Paolo Maistri, Diego Alberto, 2014, 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Countermeasures against EM analysis for a secured FPGA-based AES implementation

Israel Koren, Régis Leveugle, Philippe Maurine, 2013, 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig).

Secure Test with RSNs: Seamless Authenticated Extended Confidentiality

Régis Leveugle, Paolo Maistri, Michele Portolan, 2021, 2021 19th IEEE International New Circuits and Systems Conference (NEWCAS).

High-level fault injection to assess FMEA on critical systems

Régis Leveugle, Vincent Beroulle, Lilian Bossuet, 2021, Microelectronics Reliability.