N. A. Sherwani

Clock layout for high-performance ASIC based on weighted center algorithm

N. A. Sherwani, B. Wu, 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

New lower bounds for single row routing problems

J. S. Deogun, N. A. Sherwani, 1989, Proceedings of the 32nd Midwest Symposium on Circuits and Systems,.

A graph theoretic approach to single row routing problems

Jitender S. Deogun, Bhargab B. Bhattacharya, N. A. Sherwani, 1988, 1988., IEEE International Symposium on Circuits and Systems.