Myeong-Eun Hwang

发表

Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies

Kaushik Roy, Arijit Raychowdhury, Myeong-Eun Hwang, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

A 0.94 μW 611 KHz In-Situ Logic Operation in Embedded DRAM Memory Arrays in 90 nm CMOS

Sungoh Kwon, Myeong-Eun Hwang, 2019 .

Supply-Voltage Scaling Close to the Fundamental Limit Under Process Variations in Nanometer Technologies

Myeong-Eun Hwang, 2011, IEEE Transactions on Electron Devices.

Process-Tolerant Ultralow Voltage Digital Subthreshold Design

Myeong-Eun Hwang, K. Roy, J.P. Kulkarni, 2008, 2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

Process Tolerant 3-ratio Modulation forUltra-Dynamic Voltage Scaling

Myeong-Eun Hwang, 2007 .

Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation

Kaushik Roy, Seong-Ook Jung, Myeong-Eun Hwang, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Model for CMOS Logic Gates with Scaled Supply Voltage

Seong-Ook Jung, Kaushik Roy, Myeong-Eun Hwang, 2007 .

Energy-recovery techniques to reduce on-chip power density in molecular nanotechnologies

Arijit Raychowdhury, Myeong-Eun Hwang, Kairshik Roy, 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology

Kaushik Roy, Myeong-Eun Hwang, K. Roy, 2008, 2008 IEEE Custom Integrated Circuits Conference.

ABRM: Adaptive $ \beta$-Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling

Kaushik Roy, Myeong-Eun Hwang, K. Roy, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Process Tolerant ß-ratio Modulation for Ultra-Dynamic Voltage Scaling

Myeong-Eun Hwang, K. Roy, T. Cakici, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates

Kaushik Roy, Seong-Ook Jung, Myeong-Eun Hwang, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

Ultralow power and process variation tolerant VLSI circuit design in nano-scale technologies

Myeong-Eun Hwang, 2007 .

Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling

Kaushik Roy, Myeong-Eun Hwang, Tamer Cakici, 2007, DATE.

A 85mV 40nW Process-Tolerant Subthreshold 8×8 FIR Filter in 130nm Technology

Myeong-Eun Hwang, K. Roy, A. Raychowdhury, 2007, 2007 IEEE Symposium on VLSI Circuits.

DPFFs: C2MOS Direct Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling

Sungoh Kwon, Myeong-Eun Hwang, 2016, J. Electr. Comput. Eng..