K. Eikyu

70 nm SOI-CMOS of 135 GHz f/sub max/ with dual offset-implanted source-drain extension structure for RF/analog and logic applications

T. Iwamatsu, S. Maegawa, S. Maeda, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

A Robust SOI SRAM Architecture by using Advanced ABC technology for 32nm node and beyond LSTP devices

M. Yabuuchi, T. Iwamatsu, S. Obayashi, 2007, 2007 IEEE Symposium on VLSI Technology.

Application of a statistical compact model for Random Telegraph Noise to scaled-SRAM Vmin analysis

K. Eikyu, T. Okagaki, M. Tanizawa, 2010, 2010 Symposium on VLSI Technology.

Global Identification of Variability Factors and Its Application to the Statistical Worst-Case Model Generation

K. Eikyu, T. Okagaki, M. Tanizawa, 2006, 2006 International Conference on Simulation of Semiconductor Processes and Devices.

Circuit Technologies for Reducing the Power of SOC and Issues on Transistor Models

M. Miyazaki, K. Eikyu, Y. Tsukamoto, 2006, 2006 International Electron Devices Meeting.

Test structure measuring inter- and intralayer coupling capacitance of interconnection with subfemtofarad resolution

K. Eikyu, T. Watanabe, K. Ishikawa, 2004, IEEE Transactions on Electron Devices.

80 nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process

Masahide Inuishi, K. Eikyu, Akinobu Teramoto, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

A quantitative analysis of time-decay reproducible stress-induced leakage current in SiO/sub 2/ films

K. Eikyu, N. Ajika, K. Ishikawa, 1997 .

Non-destructive inverse modeling of copper interconnect structure for 90nm technology node

K. Eikyu, T. Watanabe, K. Ishikawa, 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..