H. Terletzki

A 220-mm/sup 2/, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture

Martin Gall, John K. DeBrosse, Oliver Kiehl, 1998 .

Developing aged SPICE model for hot carrier reliability simulation

H. Terletzki, Qiuyi Ye, W. Tonti, 2000, 2000 IEEE International Integrated Reliability Workshop Final Report (Cat. No.00TH8515).

TP 5.4: A 220mm2 4 and 8 Bank 256Mb SDRAM with Single-Sided Stitched WL Architecture

Martin Gall, John K. DeBrosse, Toshiaki Kirihata, 1998 .

Electrostatic discharge test structures for CMOS circuits

L. Risch, H. Terletzki, 1989, Proceedings of the 1989 International Conference on Microelectronic Test Structures.

A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

T. Kirihata, H. Terletzki, C. Radens, 2000, IEEE Journal of Solid-State Circuits.

A 390 mm/sup 2/ 16-bank 1 Gb DDR SDRAM with hybrid bitline architecture

G. Daniel, M. Wordeman, T. Kirihata, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).