P. Batra

Novel Test Infrastructure and Methodology Used for Accelerated Bring-Up and In-System Characterization of the Multi-Gigahertz Interfaces on the Cell Processor

P. Yeung, A. Torres, P. Batra, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

A process independent 800 MB/s DRAM bytewide interface featuring command interleaving and concurrent memory operation

P. Batra, M. Ching, M. Griffin, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).