Julen Gomez-Cornejo

Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor

Unai Bidarte, Jaime Jimenez, Aitzol Zuloaga, 2013, IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society.

Interface tasks oriented 8-bit soft-core processor

Unai Bidarte, Jaime Jimenez, Aitzol Zuloaga, 2012 .

粗粒TMR保護された部分的に再構成可能なFPGA設計における故障プロセッサの同期化【Powered by NICT】

Armando Astarloa, Unai Bidarte, Julen Gomez-Cornejo, 2016 .

Estimating the SEU failure rate of designs implemented in FPGAs in presence of MCUs

Armando Astarloa, Unai Bidarte, Jesús Lázaro, 2017, Microelectron. Reliab..

Dependability in FPGAs, a Review

Jesus Lazaro, Unai Bidarte, Julen Gomez-Cornejo, 2015, 2015 Conference on Design of Circuits and Integrated Systems (DCIS).

FPGA構成ビットストリームに基づく新しいBRAM含量アクセスと処理法【Powered by NICT】

J. Del Ser, Aitzol Zuloaga, Julen Gomez-Cornejo, 2017 .

A versatile FPGA demonstration platform for academic use

Armando Astarloa, Naiara Moreira, Unai Bidarte, 2014, 2014 XI Tecnologias Aplicadas a la Ensenanza de la Electronica (Technologies Applied to Electronics Teaching) (TAEE).

A novel BRAM content accessing and processing method based on FPGA configuration bitstream

Javier Del Ser, Jesús Lázaro, Aitzol Zuloaga, 2017, Microprocess. Microsystems.

Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

Javier Del Ser, Armando Astarloa, Unai Bidarte, 2016, Reliab. Eng. Syst. Saf..

SEU emulation in industrial SoCs combining microprocessor and FPGA

Unai Bidarte, Jaime Jimenez, Julen Gomez-Cornejo, 2018, Reliab. Eng. Syst. Saf..

Effect of different design stages on the SEU failure rate of FPGA systems

Unai Bidarte, Jaime Jiménez, Julen Gomez-Cornejo, 2016, 2016 Conference on Design of Circuits and Integrated Systems (DCIS).