A. Vais

3D technologies for analog/RF applications

P. Wambacq, B. Parvais, A. Vandooren, 2017, 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Semiconductor Technologies for next Generation Mobile Communications

P. Wambacq, B. Parvais, A. Vandooren, 2018, 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Fabrication challenges and opportunities for high-mobility materials: from CMOS applications to emerging derivative technologies

A. Vais, N. Collaert, N. Horiguchi, 2019, Advanced Lithography.

First demonstration of III-V HBTs on 300 mm Si substrates using nano-ridge engineering

M. Ingels, B. Parvais, L. Witters, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

BTI reliability of high-mobility channel devices: SiGe, Ge and InGaAs

B. Kaczer, T. Grasser, L. Witters, 2014, 2014 IEEE International Integrated Reliability Workshop Final Report (IIRW).

Engineering the III-V Gate Stack Properties by Optimization of the ALD Process

Aaron Thean, Jacopo Franco, Stefan De Gendt, 2014 .

Characterization of oxide defects in InGaAs MOS gate stacks for high-mobility n-channel MOSFETs (invited)

B. Kaczer, T. Grasser, A. Vais, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Record mobility (μeff ∼3100 cm2/V-s) and reliability performance (Vov∼0.5V for 10yr operation) of In0.53Ga0.47As MOS devices using improved surface preparation and a novel interfacial layer

R. Rooyackers, A. Vais, D. Lin, 2016, 2016 IEEE Symposium on VLSI Technology.

Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

A. Vais, C. Merckling, N. Waldron, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).