D. Mocuta

发表

3D technologies for analog/RF applications

P. Wambacq, B. Parvais, A. Vandooren, 2017, 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

The impact of sequential-3D integration on semiconductor scaling roadmap

B. Parvais, A. Vandooren, J. Ryckaert, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Technology evening panel discussion transistor future; How does it evolve after FinFET Era? Tuesday, June 6, 20:00–21:30

D. Mocuta, T. Tsunomura, C. Mazure, 2017, 2017 Symposium on VLSI Technology.

A million wafer, virtual fabrication approach to determine process capability requirements for an industry-standard 5nm BEOL two-level metal flow

D. Mocuta, D. Fried, C. J. Wilson, 2016, 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

Key challenges and opportunities for 3D sequential integration

B. Parvais, A. Vandooren, J. Ryckaert, 2018, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Accurate prediction of device performance in sub-10nm WFIN FinFETs using scalpel SSRM-based calibration of process simulations

P. Eyben, D. Mocuta, J. Mitard, 2016, 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

The Complementary FET (CFET) for CMOS scaling beyond N3

G. Bouche, J. Ryckaert, D. Mocuta, 2018, 2018 IEEE Symposium on VLSI Technology.

Challenges and opportunities of vertical FET devices using 3D circuit design layouts

J. Ryckaert, E. Vecchio, N. Waldron, 2016, 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

D. Mocuta, C. Norris, C. Radens, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Improvement of the CMOS characteristics of bulk Si FinFETs by high temperature ion implantation

D. Mocuta, R. Ritzenthaler, N. Horiguchi, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

New electrical testing structures and analysis method for MOL and BEOL process diagnostics and TDDB reliability assessment

Fen Chen, M. Shinosky, D. Mocuta, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Challenges and Opportunities for Vertical Nanowire FETs: Device Design and Fabrication

J. Ryckaert, D. Mocuta, G. Eneman, 2018, Extended Abstracts of the 2018 International Conference on Solid State Devices and Materials.

RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs

B. Parvais, S. Van Elshocht, A. Brand, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Performance and electrostatic improvement by high-pressure anneal on Si-passivated strained Ge pFinFET and gate all around devices with superior NBTI reliability

L. Witters, D. Mocuta, N. Collaert, 2017, 2017 Symposium on VLSI Technology.

Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration

D. Mocuta, H. Bender, R. Ritzenthaler, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

L. Witters, D. Mocuta, N. Collaert, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D

D. Mocuta, S. Narasimha, A. Mocuta, 2002, Digest. International Electron Devices Meeting,.

Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

L. Witters, N. Waldron, D. Mocuta, 2017, IEEE Transactions on Electron Devices.

Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires

J. Ryckaert, D. Verkest, M. Badaroglu, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL

J. Gill, D. Mocuta, D. Greenlaw, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

High performance CMOS devices on SOI for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering

D. Mocuta, Y. Toyoshima, B.H. Lee, 2003, IEEE International Electron Devices Meeting 2003.

High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor

D. Mocuta, E. Maciejewski, E. Leobandung, 2008, 2008 IEEE International Electron Devices Meeting.

3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability

B. Parvais, A. Vandooren, G. Hellings, 2018, 2018 IEEE Symposium on VLSI Technology.

Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

M. Badaroglu, L. Witters, D. Mocuta, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers

B. Parvais, A. Vandooren, J. Ryckaert, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Novel junction design for NMOS Si Bulk-FinFETs with extension doping by PEALD phosphorus doped silicate glass

D. Mocuta, R. Ritzenthaler, W. Vandervorst, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Moving Spins From Lab to Fab: A Silicon-Based Platform for Quantum Computing Device Technologies

B. Govoreanu, D. Mocuta, Ts. Ivanov, 2019, 2019 Silicon Nanoelectronics Workshop (SNW).

12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices

D. Mocuta, J. Mitard, F. Masuoka, 2019, 2019 Symposium on VLSI Technology.