Jih-Sheng Shen

发表

Network-on-Chip router design with Buffer-Stealing

Jih-Sheng Shen, Pao-Ann Hsiung, Wan-Ting Su, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Fast Run-Time Power Monitoring Methodology for Embedded Systems

Jih-Sheng Shen, Kuei-Chung Chang, Tien-Fu Chen, 2006, ESA.

Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption

Chun-Hsian Huang, Jih-Sheng Shen, Pao-Ann Hsiung, 2010, J. Syst. Archit..

Crossroad System-on-Chip Communication Architecture for Low Power Embedded Systems

Jih-Sheng Shen, Kuei-Chung Chang, Tien-Fu Chen, 2005, ESA.

Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes

Jih-Sheng Shen, Kuei-Chung Chang, Tien-Fu Chen, 2008, TODE.

An Adaptive Reasoning and Learning Framework for Mobile Cognitive Radio Systems

Jih-Sheng Shen, Pao-Ann Hsiung, Sao-Jie Chen, 2012 .

UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems

Chun-Hsian Huang, Jih-Sheng Shen, Pao-Ann Hsiung, 2008, 2008 13th Asia-Pacific Computer Systems Architecture Conference.

Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs

Jih-Sheng Shen, Kuei-Chung Chang, Tien-Fu Chen, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

PRESSNoC: Power-Aware and Reliable Encoding Schemes Supported Reconfigurable Network-on-Chip Architecture

Chun-Hsian Huang, Jih-Sheng Shen, Pao-Ann Hsiung, 2009, 2009 Fourth International Conference on Embedded and Multimedia Computing.

Dynamic Reconfigurable Network-on-Chip Design - Innovations for Computational Processing and Communication

Jih-Sheng Shen, Pao-Ann Hsiung, Pao-Ann Hsiung, 2010 .

Learning-based adaptation to applications and environments in a reconfigurable Network-on-Chip

Chun-Hsian Huang, Jih-Sheng Shen, Pao-Ann Hsiung, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Reasoning and Learning-Based Dynamic Codec Reconfiguration for Varying Processing Requirements in Network-on-Chip

Jih-Sheng Shen, Pao-Ann Hsiung, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Learning-based adaptation to applications and environments in a reconfigurable network-on-chip

Chun-Hsian Huang, Jih-Sheng Shen, Pao-Ann Hsiung, 2010, DATE 2010.

Dynamic partially reconfigurable architecture for fast Fourier transform computation

Jih-Sheng Shen, Pao-Ann Hsiung, Chun-Hsien Lu, 2014, Int. J. Embed. Syst..

A novel spatio-temporal adaptive bus encoding for reducing crosstalk interferences with trade-offs between performance and reliability

Jih-Sheng Shen, Pao-Ann Hsiung, Kuei-Chung Chang, 2008, 2008 13th Asia-Pacific Computer Systems Architecture Conference.

Scheduling and Placement of Hardware/Software Real-Time Relocatable Tasks in Dynamically Partially Reconfigurable Systems

Chun-Hsian Huang, Jih-Sheng Shen, Pao-Ann Hsiung, 2010, TRETS.

Reconfigurable Multi-core Architecture -- A Plausible Solution to the Von Neumann Performance Bottleneck

Jih-Sheng Shen, Pao-Ann Hsiung, Chun-Hsien Lu, 2013, 2013 IEEE 7th International Symposium on Embedded Multicore Socs.

On a design of crossroad switches for low-power on-chip communication architectures

Jih-Sheng Shen, Kuei-Chung Chang, Tien-Fu Chen, 2006, 2006 IEEE International Symposium on Circuits and Systems.

An Efficient Hardware/Software Communication Mechanism for Reconfigurable NoC

Jih-Sheng Shen, Pao-Ann Hsiung, Wei-Wen Lin, 2010 .

A low-power crossroad switch architecture and its core placement for network-on-chip

Jih-Sheng Shen, Kuei-Chung Chang, Tien-Fu Chen, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

Reconfigurable Network-on-chip design for heterogeneous multi-core system architecture

Jih-Sheng Shen, Pao-Ann Hsiung, Juin-Ming Lu, 2014, 2014 International Conference on High Performance Computing & Simulation (HPCS).

Spatio-Temporally-Shared Reconfigurable Fast Fourier Transform architecture design

Jih-Sheng Shen, Pao-Ann Hsiung, Chun-Hsien Lu, 2013, 2013 International Conference on Field-Programmable Technology (FPT).