T. Abe

Reduction of Vth variation by work function optimization for 45-nm node SRAM cell

Y. Akiyama, K. Imai, Y. Yamagata, 2008, 2008 Symposium on VLSI Technology.

A Cost-Effective LOP/LSTP Integrated CMOS Platform Utilizing Multi-Thickness SiON Gate Dielectrics with Hafnium for 45-nm Node

H. Nakamura, G. Tsutsui, T. Abe, 2007, 2007 IEEE Symposium on VLSI Technology.