T. Fukase

Reduction of Vth variation by work function optimization for 45-nm node SRAM cell

Y. Akiyama, K. Imai, Y. Yamagata, 2008, 2008 Symposium on VLSI Technology.

A Cost-Effective LOP/LSTP Integrated CMOS Platform Utilizing Multi-Thickness SiON Gate Dielectrics with Hafnium for 45-nm Node

H. Nakamura, G. Tsutsui, T. Abe, 2007, 2007 IEEE Symposium on VLSI Technology.

A 250 Mb/s 1 Gb double data rate SDRAM with a bi-directional delay and an inter-bank shared redundancy scheme

Y. Takai, M. Fujita, H. Ohkubo, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

55nm CMOS Technology for Low Standby Power/Generic Applications Deploying the Combination of Gate Work Function Control by HfSiON and Stress-Induced Mobility Enhancement

K. Taniguchi, T. Iwamoto, K. Imai, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..