Jong-Jin Lee

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS

Hyun-Woo Lee, Young-Jung Choi, Byong-Tae Chung, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Experimental Study on Resistance and Running Attitude of an Amphibious Assault Vehicle with a Hydrofoil as a Trim-control Device

Seung-Jae Lee, Jung-Chun Suh, Tae-il Lee, 2017 .

A low power and high performance robust digital delay locked loop against noisy environments

Young-Jung Choi, Byong-Tae Chung, Ki-Han Kim, 2008, 2008 IEEE Asian Solid-State Circuits Conference.