Gokul Krishnan

Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs

Yu Cao, Umit Y. Ogras, Jae-sun Seo, 2020, IEEE Design & Test.

A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNNs

Umit Y. Ogras, Yu Cao, Jae-Sun Seo, 2020, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Accurate Inference with Inaccurate RRAM Devices: Statistical Data, Model Transfer, and On-line Adaptation

Rajiv V. Joshi, Karsten Beckmann, Yu Cao, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

System-Level Benchmarking of Chiplet-based IMC Architectures for Deep Neural Network Acceleration

Chaitali Chakrabarti, Ümit Y. Ogras, Yu Cao, 2021, 2021 IEEE 14th International Conference on ASIC (ASICON).

SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks

Chaitali Chakrabarti, Ümit Y. Ogras, Jae-sun Seo, 2021, ACM Trans. Embed. Comput. Syst..

Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks pdf

Chaitali Chakrabarti, Ümit Y. Ogras, Jae-sun Seo, 2021, ACM J. Emerg. Technol. Comput. Syst..

Robust RRAM-based In-Memory Computing in Light of Model Stability

Rajiv V. Joshi, Karsten Beckmann, Nathaniel C. Cady, 2021, 2021 IEEE International Reliability Physics Symposium (IRPS).