Taiki Uemura

发表

Charge-collection modeling for SER simulation in FinFETs

Jongwook Jeon, Keun-Ho Lee, Udit Monga, 2016, 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server

Yoichi Koyanagi, Taiki Uemura, Tomohiro Tanaka, 2014, IEEE Journal of Solid-State Circuits.

Robust Flip-Flop against Soft Errors for Combinational and Sequential Logic Circuits

Taiki Uemura, Yoshiharu Tosaka, Hideya Matsuyama, 2008 .

New insights into 10nm FinFET BTI and its variation considering the local layout effects

Taiki Uemura, Sangwoo Pae, Minjung Jin, 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).

Soft error rate analysis for incident angle and N-well structure dependencies using small-sized alpha source in 10nm FinFET technology

Udit Monga, Taiki Uemura, Soonyoung Lee, 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).

Investigation of logic circuit soft error rate (SER) in 14nm FinFET technology

Taiki Uemura, Soonyoung Lee, Sangwoo Pae, 2016, 2016 IEEE International Reliability Physics Symposium (IRPS).

Reliability on EUV Interconnect Technology for 7nm and beyond

Min Kim, Yongsung Ji, Taiki Uemura, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

A 10th generation 16-core SPARC64 processor for mission-critical UNIX server

Yoichi Koyanagi, Taiki Uemura, Tomohiro Tanaka, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Early Diagnosis and Prediction of Wafer Quality Using Machine Learning on sub-10nm Logic Technology

Seoung Bum Kim, Yoon Sang Cho, Hyungu Kahng, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

Critical charge dependence of correlation of different neutron sources for soft error testing

Taiki Uemura, Hiroko Mori, Yukinobu Watanabe, 2015, 2015 IEEE International Reliability Physics Symposium.

Soft error immune latch design for 20 nm bulk CMOS

Masanori Hashimoto, Taiki Uemura, Takashi Kato, 2015, 2015 IEEE International Reliability Physics Symposium.

High-accuracy estimation of soft error rate using PHYSERD with circuit simulation

Takashi Kato, Taiki Uemura, Hideya Matsuyama, 2014, 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

Investigation of single event upset and total ionizing dose in FeRAM for medical electronic tag

Masanori Hashimoto, Taiki Uemura, 2015, 2015 IEEE International Reliability Physics Symposium.

Backside Alpha-Irradiation Test in Flip-Chip Package in EUV 7 nm FinFET SRAM

Seungbae Lee, Yongsung Ji, Taiki Uemura, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

Scaling Trends and Mitigation Techniques for Soft Errors in Flip-Flops

Taiki Uemura, Yoshiharu Tosaka, Keiji Takahisa, 2006 .

Novel Soft Error Hardened Latches and Flip-Flops

Taiki Uemura, Ryo Tanabe, Yoshiharu Tosaka, 2007 .

Using Low Pass Filters in Mitigation Techniques against Single-Event Transients in 45nm Technology LSIs

Taiki Uemura, Ryo Tanabe, Yoshiharu Tosaka, 2008, 2008 14th IEEE International On-Line Testing Symposium.

Investigating of SER in 28 nm FDSOI-Planar and Comparing with SER in Bulk-FinFET

Youngin Park, Seungbae Lee, Yongsung Ji, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

Advanced Self-heating Model and Methodology for Layout Proximity Effect in FinFET Technology

Yongsung Ji, Taiki Uemura, Sangwoo Pae, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

Investigation of multi cell upset in sequential logic and validity of redundancy technique

Taiki Uemura, Takashi Kato, Hideya Matsuyama, 2011, 2011 IEEE 17th International On-Line Testing Symposium.

Layout optimization to maximize tolerance in SEILA: Soft error immune latch

Taiki Uemura, Hideya Matsuyama, Tsunehisa Sakoda, 2011, 2011 IEEE International Conference on IC Design & Technology.

Investigation of alpha-induced single event transient (SET) in 10 nm FinFET logic circuit

Seungbae Lee, Taiki Uemura, Soonyoung Lee, 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

Investigation of logic soft error and scaling effect in 10 nm FinFET technology

Taiki Uemura, Soonyoung Lee, Sangwoo Pae, 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).

Impact of package on neutron induced single event upset in 20 nm SRAM

Masanori Hashimoto, Taiki Uemura, Takashi Kato, 2015, 2015 IEEE International Reliability Physics Symposium.

Robust Flip-Flop Circuit against Soft Errors for Combinational and Sequential Logic Circuits

Taiki Uemura, Yoshiharu Tosaka, Hideya Matsuyama, 2009 .

Reliability characterization of 10nm FinFET technology with multi-VT gate stack for low power and high performance

Taiki Uemura, Soonyoung Lee, Sangwoo Pae, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

SEIFF: Soft Error Immune Flip-Flop for Mitigating Single Event Upset and Single Event Transient in 10 nm FinFET

Seungbae Lee, Taiki Uemura, Soonyoung Lee, 2019, 2019 IEEE International Reliability Physics Symposium (IRPS).

Mitigating Multi-Bit-Upset With Well-Slits in 28 nm Multi-Bit-Latch

Masanori Hashimoto, Takashi Kato, Taiki Uemura, 2013, IEEE Transactions on Nuclear Science.

Soft-Error Susceptibility in Flip-Flop in EUV 7 nm Bulk-FinFET Technology

Taiki Uemura, Jeongmin Jo, Gunrae Kim, 2021, 2021 IEEE International Reliability Physics Symposium (IRPS).

Soft Error Hardened Latch and Its Estimation Method

Taiki Uemura, Ryo Tanabe, Yoshiharu Tosaka, 2008 .

Neutron-Induced Soft-Error Simulation Technology for Logic Circuits

Taiki Uemura, Yoshiharu Tosaka, Shigeo Satoh, 2006 .

Measurement of neutron-induced single event transient pulse width narrower than 100ps

Shigetaka Kumashiro, Taiki Uemura, Katsuhiko Tanaka, 2010, 2010 IEEE International Reliability Physics Symposium.

Origin analysis of thermal neutron soft error rate at nanometer scale

Yuji Kataoka, Taiki Uemura, Takeshi Soeda, 2015 .

Technology Scaling Trend of Soft Error Rate in Flip-Flops in $1\times$ nm Bulk FinFET Technology

Taiki Uemura, Soonyoung Lee, Sangwoo Pae, 2018, IEEE Transactions on Nuclear Science.

Multi-scale Monte Carlo simulation of soft errors using PHITS-HyENEXSS code system

Nobuyuki Sano, Taiki Uemura, Yukinobu Watanabe, 2011, 2011 12th European Conference on Radiation and Its Effects on Components and Systems.

Study on Influence of Device Structure Dimensions and Profiles on Charge Collection Current Causing SET Pulse Leading to Soft Errors in Logic Circuits

Shigetaka Kumashiro, Taiki Uemura, Katsuhiko Tanaka, 2009, 2009 International Conference on Simulation of Semiconductor Processes and Devices.

Radiation-Induced Parasitic Bipolar Effect in PMOS with Embedded SiGe

Taiki Uemura, Hideya Matsuyama, S. Satoh, 2012 .

Soft-Error in SRAM at Ultra-Low Voltage and Impact of Secondary Proton in Terrestrial Environment

Masanori Hashimoto, Taiki Uemura, Hideya Matsuyama, 2013, IEEE Transactions on Nuclear Science.

Neutron-induced Soft-Error Simulation Technology for Logic Circuits

Taiki Uemura, Yoshiharu Tosaka, Shigeo Satoh, 2005 .

Exploring Well-Configurations for Minimizing Single Event Latchup

Masanori Hashimoto, Taiki Uemura, Ryo Tanabe, 2014, IEEE Transactions on Nuclear Science.

Impact of Parasitic Bipolar Effect on Single-Event Upset in p-Type Metal–Oxide–Semiconductor Field Effect Transistor with Embedded SiGe

Taiki Uemura, S. Satoh, Y. Ikeda, 2013 .