J. Newbury

A 0.021 µm2 trigate SRAM cell with aggressively scaled gate and contact pitch

V. Narayanan, M. Khater, I. Lauer, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS)

M. Ieong, W. Haensch, J. Kedzierski, 2003, IEEE International Electron Devices Meeting 2003.

Effective Schottky Barrier lowering for contact resistivity reduction using silicides as diffusion sources

P. M. Solomon, J. J. Bucchignano, J. Bruley, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Systematic study of work function engineering and scavenging effect using NiSi alloy FUSI metal gates with advanced gate stacks

Y.H. Kim, V. Narayanan, R. Carruthers, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Poly-Si/AlN/HfSiO Stack for Ideal Threshold Voltage and Mobility in Sub-100 nm MOSFETs

P. Oldiges, V. Narayanan, M. Steen, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Systematic study of pFET V/sub t/ with Hf-based gate stacks with poly-Si and FUSI gates

V. Narayanan, R. Carruthers, M. Steen, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Silicon-on-Insulator MOSFETs with Hybrid Crystal Orientations

J. Patel, J. Sleight, M. Ieong, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Aggressively scaled (0.143 /spl mu/m/sup 2/) 6T-SRAM cell for the 32 nm node and beyond

M. Ieong, O. Dokumaci, W. Haensch, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Charge trapping in aggressively scaled metal gate/high-k stacks

K. Maitra, V. Narayanan, R. Carruthers, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..