K. Teranishi

A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor

T. Kataoka, K. Nii, T. Saito, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Multiple-valued logic-in-memory VLSI based on a floating-gate-MOS pass-transistor network

T. Hanyu, M. Kameyama, K. Teranishi, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).