Javier Castro-Ramirez

Reducing bit flipping problems in SRAM physical unclonable functions for chip identification

Piedad Brox Jiménez, Iluminada Baturone, Susana Eiroa, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures

Antonio J. Acosta, Javier Castro-Ramirez, Pilar Parra Fernández, 2009, PATMOS.

A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions

Piedad Brox Jiménez, Iluminada Baturone, Antonio J. Acosta, 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits

Erica Tena-Sánchez, Antonio J. Acosta, Javier Castro-Ramirez, 2014, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

A switching noise vision of the optimization techniques for low-power synthesis

Javier Castro-Ramirez, Manuel Valencia-Barrero, Pilar Parra Fernández, 2007, 2007 18th European Conference on Circuit Theory and Design.

Optimization of Master-Slave Flip-Flops for High-Performance Applications

Manuel Sanchez-Raya, Raúl Jiménez, Antonio J. Acosta, 2006, PATMOS.

Optimization of clock-gating structures for low-leakage high-performance applications

Antonio J. Acosta, Javier Castro-Ramirez, Pilar Parra Fernández, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Asymmetric clock driver for improved power and noise performances

Antonio J. Acosta, Javier Castro-Ramirez, Manuel Valencia-Barrero, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Low-Power Differential Logic Gates for DPA Resistant Circuits

Erica Tena-Sánchez, Antonio J. Acosta, Javier Castro-Ramirez, 2014, 2014 17th Euromicro Conference on Digital System Design.

Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications

Erica Tena-Sánchez, Antonio J. Acosta, Javier Castro-Ramirez, 2014, 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

ASIC-in-the-loop methodology for verification of piecewise affine controllers

Piedad Brox Jiménez, Iluminada Baturone, Antonio J. Acosta, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).