Koji Sakui

High Speed, Low Power, and Ultra-Small Operating Platform with Three-Dimensional Integration (3DI) by Bumpless Interconnects

Koji Sakui, Takayuki Ohba, T. Ohba, 2019, 2019 IEEE 11th International Memory Workshop (IMW).

Three-dimensional Integration (3DI) with Bumpless Interconnects for Tera-scale Generation : High Speed, Low Power, and Ultra-small Operating Platform

Koji Sakui, Takayuki Ohba, T. Ohba, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

A compact and low power logic design for multi-pillar vertical MOSFETs

Tetsuo Endoh, Koji Sakui, K. Sakui, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

A high-performance 1-Mbit dynamic RAM with a folded capacitor cell

Fumio Horiguchi, Mitsugi Ogura, Shigeyoshi Watanabe, 1986 .

High Bandwidth Memory (HBM) and High Bandwidth NAND (HBN) with the Bumpless TSV Technology

Koji Sakui, Takayuki Ohba, T. Ohba, 2019, 2019 International 3D Systems Integration Conference (3DIC).

Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET

Tetsuo Endoh, Koji Sakui, Yukio Yasuda, 2009, IEICE Trans. Electron..

Design of 30 nm FinFETs and Double Gate MOSFETs with Halo Structure

Tetsuo Endoh, Koji Sakui, Yukio Yasuda, 2010, IEICE Trans. Electron..

Vertically Replaceable Memory Block Architecture for Stacked DRAM Systems by Wafer-on-Wafer (WOW) Technology

Koji Sakui, Norio Chujo, Hiroyuki Ryoson, 2020, IEEE Transactions on Electron Devices.