S. Bitterlich

Trellis pipeline-interleaving: a novel method for efficient Viterbi decoder implementation

Heinrich Meyr, H. Dawid, S. Bitterlich, 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

Boosting the implementation efficiency of Viterbi decoders by novel scheduling schemes

Heinrich Meyr, H. Dawid, S. Bitterlich, 1992, [Conference Record] GLOBECOM '92 - Communications for Global Users: IEEE.

Optimizing computation and communication in shuffle-exchange processors

Gerhard Fettweis, S. Bitterlich, 1991, [1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems.