Bahram Pouya

Synthesis of zero-aliasing elementary-tree space compactors

Nur A. Touba, Bahram Pouya, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

Virtual scan chains: a means for reducing scan length in cores

Nur A. Touba, Bahram Pouya, Abhijit Jas, 2000, Proceedings 18th IEEE VLSI Test Symposium.

Optimization trade-offs for vector volume and test power

Alfred L. Crouch, Bahram Pouya, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Modifying user-defined logic for test access to embedded cores

Nur A. Touba, Bahram Pouya, N. Touba, 1997, Proceedings International Test Conference 1997.

Testing embedded cores using partial isolation rings

Nur A. Touba, Bahram Pouya, N. Touba, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

Reducing power dissipation during test using scan chain disable

Nur A. Touba, Ranganathan Sankaralingam, Bahram Pouya, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

Testing Core-Based Designs Using Partial Isolation Rings

Nur A. Touba, Bahram Pouya, 2007 .

Using Partial Isolation Rings to Test Core-Based Designs

Nur A. Touba, Bahram Pouya, 1997, IEEE Des. Test Comput..

BETSY: synthesizing circuits for a specified BIST environment

Nur A. Touba, Zhe Zhao, Bahram Pouya, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Test data compression technique for embedded cores using virtual scan chains

Nur A. Touba, Bahram Pouya, Abhijit Jas, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.