Jiang Jianhui

A novel method for the construction of self-dual circuits

Wang Wei, Jiang Jianhui, 2005, 2005 6th International Conference on ASIC.

VHDL modeling and analysis of error-control specific circuits for multiple-modular redundant systems with concurrent error location capability

Jiang Jianhui, Min Yinghua, Peng Chenglian, 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).

Error-Correcting Techniques for High-Performance Processors

Jiang Jianhui, Wang Zhen, Yuan Chunxin, 2008 .

Simulation-Based Non-Linear Methods for the Estimation of Execution Cycles of ARM Programs

Jiang Jianhui, Kong Liangliang, Xiao Jie, 2012 .

Performance Assessment of Embedded Systems by Benchmarking

Jiang Jianhui, 2002 .

Power-constrained SoC test scheduling optimization using asynchronous clock periods

Ling Li, Jiang Jianhui, Jiang Jianhui, 2015 .

A new soft IP core for online-testing and fault-tolerant structures

Wang Wei, Jiang Jianhui, 2007, 2007 7th International Conference on ASIC.

Software Reliability Prediction Modeling with Relevance Vector Machine

Jiang Yunliang, Jiang Jianhui, Lou Jungang, 2013 .

Fault tolerance and pipelining of VLSI combinational logic networks

Jiang Jianhui, Hu Mou, 1993, Proceedings of TENCON '93. IEEE Region 10 International Conference on Computers, Communications and Automation.