S. Sauter

Measurement and simulation of interconnect capacitance variations

D. Schmitt-Landsiedel, R. Thewes, S. Sauter, 2000, 2000 5th International Workshop on Statistical Metrology (Cat.No.00TH8489.

Clock skew determination from parameter variations at chip and wafer level

D. Schmitt-Landsiedel, W. Weber, D. Cousinard, 1999, 1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391).

What Do Matching Results of Medium Area MOSFETs Reveal for Large Area Devices in Typical Analog Applications

G. Knoblinger, R. Thewes, U. Kollmer, 1998, 28th European Solid-State Device Research Conference.

Effect of parameter variations at chip and wafer level on clock skews

Doris Schmitt-Landsiedel, Roland Thewes, S. Sauter, 2000 .