Emerson S. Fang

32-nm SOI programmable, high-bandwidth 8.0-GHz digital PLL

Sanjeev K. Maheshwari, Emerson S. Fang, Sanjeev K. Aggarwal, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

Bridging design and manufacture of analog/mixed-signal circuits in advanced CMOS

Jung-Suk Goo, Zhi-Yuan Wu, Jia Feng, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors

Sanjeev K. Maheshwari, Emerson S. Fang, Sanjeev K. Aggarwal, 2011, IEEE Asian Solid-State Circuits Conference 2011.

Loopback architecture for wafer-level at-speed testing of embedded HyperTransportTM processor links

Emerson S. Fang, Alvin Leng Sun Loke, Tin Tin Wee, 2009, 2009 IEEE Custom Integrated Circuits Conference.

A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O

Emerson S. Fang, Alvin Leng Sun Loke, Dennis Michael Fischette, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A MULTI-GIGAHERTZ JOSEPHSON FLASH AID CONVERTER USING LARGE-DYNAMIC-RANGE CURRENT-LATCH COMPARATORS WITH A PIPELINED ENCODER

Emerson S. Fang, D. Hebert, Theodore Van Duzer, 1991 .

An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors

Sanjeev K. Maheshwari, Emerson S. Fang, Alvin Leng Sun Loke, 2012, IEEE Journal of Solid-State Circuits.

Linear Equalization and PVT-Independent DC Wander Compensation for AC-Coupled PCIe 3.0 Receiver Front End

Emerson S. Fang, Jingcheng Zhuang, Bruce Andrew Doyle, 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.