R. Zambrano

发表

Improved structures for power MOSFETs with on-chip full protection

R. Zambrano, 2002 .

High Voltage IC with Vertical Current Flow and Buried Emitter optimizes Power Handling Capability.

R. Zambrano, 1989 .

Isolation Techniques in Power ICs with Vertical Current Flow

M. Paparo, S. Musumeci, G. Ferla, 1987, ESSDERC '87: 17th European Solid State Device Research Conference.