J. Etoh

An Experimental 16mb Dram with Transposed Data-Line Structure

H. Tanaka, E. Takeda, Y. Nakagome, 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

Low-power chip interconnection by dynamic termination

Takayuki Kawahara, Katsutaka Kimura, Masashi Horiguchi, 1995 .

An experimental 1 Mbit DRAM based on high S/N design

R. Hori, H. Sunami, S. Asai, 1984, IEEE Journal of Solid-State Circuits.

Dual-Regulator Dual-Decoding-Trimmer DRAM Voltage Limiter For Burn-in Test

K. Kajigaya, A. Nozoe, K. Itoh, 1991, 1991 Symposium on VLSI Circuits.

A new stacked capacitor DRAM cell characterized by a storage capacitor on a bit-line structure

E. Takeda, M. Aoki, H. Sunami, 1988, Technical Digest., International Electron Devices Meeting.

Sub-1-/spl mu/A dynamic reference voltage generator for battery-operated DRAMs

Y. Nakagome, E. Yamasaki, M. Aoki, 1993, Symposium 1993 on VLSI Circuits.

Low Power Chip Interconnection by Dynamic Termination

Masashi Horiguchi, Takayuki Kawahara, Tomonori Sekiguchi, 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier

K. Kajigaya, M. Aoki, K. Ohshima, 1990, Digest of Technical Papers., 1990 Symposium on VLSI Circuits.