A. Hikavyy

发表

First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers

J. Ryckaert, T. Chiarella, N. Horiguchi, 2020, 2020 IEEE Symposium on VLSI Technology.

High-mobility Si1−xGex-channel PFETs: Layout dependence and enhanced scalability, demonstrating 90% performance boost at narrow widths

C. Ortolland, L. Witters, H. Bender, 2010, 2010 Symposium on VLSI Technology.

Strained Germanium quantum well pMOS FinFETs fabricated on in situ phosphorus-doped SiGe strain relaxed buffer layers using a replacement Fin process

L. Witters, N. Waldron, N. Collaert, 2013, 2013 IEEE International Electron Devices Meeting.

Performance and reliability of high-mobility Si0.55Ge0.45 p-channel FinFETs based on epitaxial cladding of Si Fins

L. Witters, N. Collaert, H. Bender, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

High-mobility 0.85nm-EOT Si0.45Ge0.55-pFETs: Delivering high performance at scaled VDD

A. Mercha, L. Witters, J. Mitard, 2010, 2010 International Electron Devices Meeting.

Full-field EUV and immersion lithography integration in 0.186μm2 FinFET 6T-SRAM cell

B. Parvais, R. Rooyackers, K. Ronse, 2008, 2008 IEEE International Electron Devices Meeting.

High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout

K. Ronse, S. Locorotondo, V. Truffert, 2010, 2010 Symposium on VLSI Technology.

8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS

L. Witters, H. Bender, T. Chiarella, 2010, 2010 Symposium on VLSI Technology.

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

L. Witters, D. Mocuta, N. Collaert, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

A. Brand, P. Eyben, L. Witters, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

1mA/um-ION strained SiGe45%-IFQW pFETs with raised and embedded S/D

P. Eyben, G. Hellings, L. Witters, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

L. Witters, N. Waldron, D. Mocuta, 2017, IEEE Transactions on Electron Devices.

3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability

B. Parvais, A. Vandooren, G. Hellings, 2018, 2018 IEEE Symposium on VLSI Technology.

Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

M. Badaroglu, L. Witters, D. Mocuta, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers

B. Parvais, A. Vandooren, J. Ryckaert, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Standard cell level parasitics assessment in 20nm BPL and 14nm BFF

A. Mercha, D. Verkest, M. Badaroglu, 2012, International Electron Devices Meeting.

Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

R. Rajagopalan, K. Ronse, S. Locorotondo, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Challenges for introducing Ge and III/V devices into CMOS technologies

B. Kaczer, G. Hellings, L. Witters, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

Layout Scaling of $\hbox{Si}_{1-x}\hbox{Ge}_{x} \hbox{-Channel}$ pFETs

C. Ortolland, L. Witters, J. Mitard, 2011, IEEE Transactions on Electron Devices.