A. Suzuki

A 0.7V single-supply SRAM with 0.495um2 cell in 65nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme

T. Sasaki, K. Kushida, A. Suzuki, 2008, 2008 IEEE Symposium on VLSI Circuits.

A 0.7 V Single-Supply SRAM With 0.495 $\mu$m$^{2}$ Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

T. Sasaki, K. Kushida, A. Suzuki, 2009, IEEE Journal of Solid-State Circuits.

A 65nm low-power embedded DRAM with extended data-retention sleep mode

A. Suzuki, T. Hojo, T. Miyazaki, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.