Paolo Mantovani

发表

System-level design of networks-on-chip for heterogeneous systems-on-chip

Luca P. Carloni, Young-Jin Yoon, Paolo Mantovani, 2017, 2017 Eleventh IEEE/ACM International Symposium on Networks-on-Chip (NOCS).

An analysis of accelerator coupling in heterogeneous architectures

Luca P. Carloni, Giuseppe Di Guglielmo, Paolo Mantovani, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Accelerators and Coherence: An SoC Perspective

Luca P. Carloni, Paolo Mantovani, Davide Giri, 2018, IEEE Micro.

High-level synthesis of accelerators in embedded scalable platforms

Luca P. Carloni, Giuseppe Di Guglielmo, Paolo Mantovani, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI

Luca P. Carloni, Kenneth L. Shepard, Angel V. Peterchev, 2012, IEEE Journal of Solid-State Circuits.

System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip

Luca P. Carloni, Christian Pilato, Paolo Mantovani, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration

Luca P. Carloni, Paolo Mantovani, Emilio G. Cota, 2016, ICS.

Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case study

Mario R. Casu, Stefano Colazzo, Paolo Mantovani, 2011, GLSVLSI '11.

Runtime reconfigurable memory hierarchy in embedded scalable platforms

Luca P. Carloni, Paolo Mantovani, Davide Giri, 2019, ASP-DAC.

COSMOS

Luca P. Carloni, Luca Piccolboni, Giuseppe Di Guglielmo, 2017, ACM Trans. Embed. Comput. Syst..

On the design of scalable and reusable accelerators for big data applications

Luca P. Carloni, Christian Pilato, Giuseppe Di Guglielmo, 2016, Conf. Computing Frontiers.

Scalable System-on-Chip Design

Paolo Mantovani, 2017 .

A synchronous latency-insensitive RISC for better than worst-case design

Mario R. Casu, Paolo Mantovani, 2015, Integr..

On maximal intermediate predicate constructive logics

Pierangelo Miglioli, Camillo Fiorentini, Alessandro Avellone, 1996, Stud Logica.

System-level memory optimization for high-level synthesis of component-based SoCs

Luca P. Carloni, Christian Pilato, Giuseppe Di Guglielmo, 2014, 2014 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip

Luca P. Carloni, Christian Pilato, Giuseppe Di Guglielmo, 2016, 2016 International Conference on Compliers, Architectures, and Sythesis of Embedded Systems (CASES).

Broadening the exploration of the accelerator design space in embedded scalable platforms

Luca P. Carloni, Luca Piccolboni, Giuseppe Di Guglielmo, 2017, 2017 IEEE High Performance Extreme Computing Conference (HPEC).

NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators

Luca P. Carloni, Paolo Mantovani, Davide Giri, 2018, 2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS).

Accelerator Memory Reuse in the Dark Silicon Era

Luca P. Carloni, Mario R. Casu, Paolo Mantovani, 2014, IEEE Computer Architecture Letters.

An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems

Luca P. Carloni, Kenneth L. Shepard, Christian Pilato, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Accelerator Integration for Open-Source SoC Design

Luca P. Carloni, Paolo Mantovani, Davide Giri, 2021, IEEE Micro.

Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs

Luca P. Carloni, Paolo Mantovani, Davide Giri, 2021, MICRO.

COSMOS

Luca P. Carloni, Luca Piccolboni, Giuseppe Di Guglielmo, 2017, CABI Compendium.