Keisuke Inoue

发表

An ILP-based Optimization Method for Radiation Hardened Register and ECC Mixed Architectures

Keisuke Inoue, 2019, 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC).

Variable-duty-cycle scheduling in double-edge-triggered flip-flop-based high-level synthesis

Keisuke Inoue, Mineo Kaneko, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Social dynamics of free and open source team communications

Kevin Crowston, James Howison, Keisuke Inoue, 2006, OSS.

Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range

Keisuke Inoue, Mineo Kaneko, M. Kaneko, 2012, 17th Asia and South Pacific Design Automation Conference.

Estimation of Fading Characteristics Based on Received Signals at Multiple Different Locations

Hisato Iwai, Hideichi Sasaoka, Keisuke Inoue, 2007 .

Keisuke Inoue, Mineo Kaneko, M. Kaneko, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

Minimizing clocking patterns of Adjustable safe clocking for timing variation-aware datapaths

Keisuke Inoue, Mineo Kaneko, 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

Discourse analysis of online chat reference interviews for modeling online information-seeking dialogues

Keisuke Inoue, Keisuke Inoue, 2009, ASIST.

Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation

Keisuke Inoue, Mineo Kaneko, 2011, IPSJ Trans. Syst. LSI Des. Methodol..

Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis

Keisuke Inoue, Mineo Kaneko, 2012, GLSVLSI '12.

A 250-MHz single-chip multiprocessor for audio and video signal processing

Keisuke Inoue, H. Hanaki, E. Iwata, 2001 .

Upgrading RDF stores in National Bioscience Database Centers

Keisuke Inoue, Shigeru Yatsuzuka, Takehiro Kato, 2016 .

AN EXPERIMENT FOR FORMING A COMMUNITY-VISIONING THROUGH MULTI-STAGE QUESTIONNAIRES METHOD-A case study of Shirakabe-Chikara-Shumoku historic preservation district-

Keisuke Inoue, Teruhiko Yoshimura, Toshiyuki Kaneda, 2008 .

Real Time Parallel Image Processing Using a Silicon Retina and FPGA Circuits

Keisuke Inoue, Tetsuya Yagi, Seiji Kameda, 2007 .

A real-time target tracking employing a silicon retina

Keisuke Inoue, Tetsuya Yagi, Kazuhiro Shimonomura, 2003 .

Web-site Visualization Using Dynamics-based Model

Keisuke Inoue, Takayuki Itoh, Yuko Ikehata, 2001 .

Tracking a Moving Object Employing a Silicon Retina and FPGA Circuits

Keisuke Inoue, Tetsuya Yagi, Kazuhiro Shimonomura, 2004 .

A framework for embedded software sourcing: Another strategic sourcing in the electronics industry

Keisuke Inoue, Yasuo Ikawa, 2013, 2013 Proceedings of PICMET '13: Technology Management in the IT-Driven Services (PICMET).

A cache coherency protocol for multiprocessor chip

Hideharu Amano, Keisuke Inoue, Takuya Terasawa, 1995, Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI).

Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths

Keisuke Inoue, Tsuyoshi Iwagaki, Mineo Kaneko, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

2A1-C12 Depth Detection Employing a Brain-like Robot Vision

Keisuke Inoue, Tetsuya Yagi, Kazuhiro Shimonomura, 2006 .

A study on snoop cache systems for single-chip multiprocessors

Hideharu Amano, Keisuke Inoue, Takuya Terasawa, 1997, Systems and Computers in Japan.

An Approach for Generating Meshes Similar to A Reference Mesh

Keisuke Inoue, Kenji Shimada, Atsushi Yamada, 2000, IMR.

Ordered coloring-based resource binding for datapaths with improved skew-adjustability

Keisuke Inoue, Mineo Kaneko, 2011, GLSVLSI '11.

Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis

Keisuke Inoue, Tsuyoshi Iwagaki, Mineo Kaneko, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Automatic Examination-Based Whitelist Generation for XSS Attack Detection

Kohei Mukaiyama, Masakatsu Nishigaki, Keisuke Inoue, 2018, BWCCA.

Spanning Distribution Forests of Graphs - (Extended Abstract)

Keisuke Inoue, Takao Nishizeki, 2014, FAW.

Safe clocking register assignment in datapath synthesis

Keisuke Inoue, Tsuyoshi Iwagaki, Mineo Kaneko, 2008, 2008 IEEE International Conference on Computer Design.

A Novel Robot Vision Applicable to Real-time Target Tracking

Keisuke Inoue, Tetsuya Yagi, Kazuhiro Shimonomura, 2003, J. Robotics Mechatronics.

Bitwidth-aware register allocation and binding for clock period minimization

Keisuke Inoue, Mineo Kaneko, 2015, 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS).

ATTEMPT-1: A Reconfigurable Multiprocessor Testbed

Hideharu Amano, Keisuke Inoue, Michitaka Okuno, 1996, FPL.

L-031 Proposal and Implementation of A Simple Resource Assignment for the Ethernet by SIP

Keisuke Inoue, Nobuyuki Tokura, 2004 .

INFLUENCE OF ROAD SPACE REALLOCATION ON TRAFFIC FLOW

Keisuke Inoue, Jongjin Yoon, Masahiro Emori, 2012 .

A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths

Keisuke Inoue, Mineo Kaneko, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches

Keisuke Inoue, Mineo Kaneko, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Optimal stall insertion with timing skew adjustment for tunable LSIs

Keisuke Inoue, Takayuki Obata, Mineo Kaneko, 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

pSAS/c: Pseudo Set Associative and Shared with Competitive Cache

Hideharu Amano, Keisuke Inoue, 2000 .

An ILP-Based Optimal Circuit Mapping Method for PLDs

Shinobu Nagayama, Keisuke Inoue, Shin'ichi Wakabayashi, 2014, 2014 IEEE International Parallel & Distributed Processing Symposium Workshops.

Operation scheduling considering time borrowing for high-performance latch-based circuits

Keisuke Inoue, Mineo Kaneko, 2011, 2011 IEEE 9th International New Circuits and systems conference.

Reliable and low-power clock distribution using pre- and post-silicon delay adaptation in high-level synthesis

Keisuke Inoue, Mineo Kaneko, 2012, 2012 IEEE International Symposium on Circuits and Systems.

A study on snoop cache systems for single-chip multiprocessors

Hideharu Amano, Keisuke Inoue, Takuya Terasawa, 1997 .

A Face Clustering Method for a Hexahedral Meshing

Keisuke Inoue, Atsushi Yamada, Jun Doi, 2003, DAC 2003.

Investigation and trend analysis of external links and downloadable datasets in life science databases

Keisuke Inoue, Shinichi Hirai, Toshihisa Takagi, 2015 .

Automated Detection of Subject Area for Question Triage in Digital Reference

Keisuke Inoue, 2009 .

Early planning for RT-level delay insertion during clock skew-aware register binding

Keisuke Inoue, Mineo Kaneko, 2011, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip.

Removing Reflection from In-vehicle Camera Image

Keisuke Inoue, Fumihiko Sakaue, Jun Sato, 2020, VISIGRAPP.

An Investigation of Digital Reference Interviews: A Dialogue Act Approach.

Keisuke Inoue, Keisuke Inoue, 2013 .

A dependable ASIC architecture with RT-level rollback for controller soft error recovery

Keisuke Inoue, 2017, 2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).

Safe clocking for the setup and hold timing constraints in datapath synthesis

Keisuke Inoue, Tsuyoshi Iwagaki, Mineo Kaneko, 2009, GLSVLSI '09.

Novel Register Sharing in Datapath for Structural Robustness against Delay Variation

Keisuke Inoue, Tsuyoshi Iwagaki, Mineo Kaneko, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Knowledge Discovery from Heterogeneous Dynamic Systems using Change-Point Correlations

Keisuke Inoue, Tsuyoshi Idé, T. Idé, 2005, SDM.

Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle

Keisuke Inoue, Mineo Kaneko, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths

Keisuke Inoue, Mineo Kaneko, 2010, GLSVLSI '10.

Automated Keyword Extraction of Learning Materials Using Semantic Relations

Keisuke Inoue, Nancy McCracken, 2010 .

Discussion about the geophysical exploration ten years later —Special session for SEGJ 65th anniversary—

Keisuke Inoue, Kentaro Torii, Takeshi Yoshikawa, 2013 .

ISIS: Multiprocessor Simulator Library

Hideharu Amano, Keisuke Inoue, Masaki Wakabayashi, 1999, Applied Informatics.

Proceedings of the 46th Annual Meeting of the Association for Computational Linguistics on Human Language Technologies: Student Research Workshop

Ebru Arisoy, Keisuke Inoue, Wolfgang Maier, 2008 .

Automated Conversion of 2D Triangular Mesh into Quadrilateral Mesh with Directionality Control

Keisuke Inoue, Kenji Shimada, Atsushi Yamada, 1998, IMR.

A-1-31 A Note on Sparse Networks Tolerating Random Faults for Cycles(A-1. 回路とシステム, 基礎・境界)

Keisuke Inoue, Kumiko Nomura, Satoshi Tayu, 2005 .

Clustering Large Number of Faces for 2-Dimensional Mesh Generation

Keisuke Inoue, Kenji Shimada, Atsushi Yamada, 1999, IMR.

Delay Variability-Aware Datapath Synthesis Based on Safe Clocking for Setup and Hold Timing Constraints

Keisuke Inoue, Tsuyoshi Iwagaki, Mineo Kaneko, 2008 .

Case Study of the Rantau Waterflooding Project

Keisuke Inoue, Yul Tri Ananto, 1987 .

Experimental Determination of Effective Attenuation Length for SiO2 Thin Film with Synchrotron Radiation Photoemission Spectroscopy

Keisuke Inoue, Yuden Teraoka, Y. Teraoka, 2010 .

Conversation Repository for Participatory Librarianship

Keisuke Inoue, Keisuke Inoue, 2008 .

Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors

Hideharu Amano, Keisuke Inoue, Junji Yamamoto, 1997, Euro-Par.

Optimal register assignment with minimum-delay compensation for latch-based design

Keisuke Inoue, Mineo Kaneko, M. Kaneko, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

Experimental study on resistivity monitoring for detection of cracks caused by earthquake

Keisuke Inoue, Hiroomi Nakazato, 2011 .

A Note on Sparse Networks Tolerating Random Faults for Cycles

Keisuke Inoue, Kumiko Nomura, Satoshi Tayu, 2005 .

ECC module optimization for storage transient error-tolerant ASICs

Keisuke Inoue, 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Real-time motion detection with a mixed analogue–digital neuromorphic vision system

Keisuke Inoue, Tetsuya Yagi, Seiji Kameda, 2007 .

Brain-like Robot Vision

S. Kameda, Keisuke Inoue, K. Shimonomura, 2002 .

EB induced tensile strengthening of CFRP

Keisuke Inoue, Yoshitake Nishi, Akira Tonegawa, 2006 .