Robert Hannon

WP 24.3 1GHz Fully Pipelined 3.7ns Address Access Time 8kx1024 Embedded DRAM Macro

Osamu Takahashi, Matthew R. Wordeman, Sang Hoo Dhong, 2000 .

Improved Drum Brake Shoe Factor Prediction with the Consideration of System Compliance

Shan Shih, Rajesh J. Somnay, Robert Hannon, 2000 .

0.25 /spl mu/m merged bulk DRAM and SOI logic using patterned SOI

Robert Hannon, D. Sadana, Subramanian S. Iyer, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).