T. Sunaga

A full bit prefetch architecture for synchronous DRAM's

Yutaka Nakamura, K. Hosokawa, M. Ichinose, 1995 .

A 30-ns cycle time 4-Mb mask ROM

T. Sunaga, 1994 .

Optimizing write current and power dissipation in MRAMs by using an astroid curve

H. Asano, H. Umezaki, T. Sunaga, 2004, IEEE Transactions on Magnetics.