Maksim Jenihhin

发表

Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2008, 2008 13th European Test Symposium.

Automated test bench generation for high-level synthesis flow ABELITE

Raimund Ubar, Jaan Raik, Samary Baranov, 2011, 2011 9th East-West Design & Test Symposium (EWDTS).

Implementation-Independent Functional Test Generation for MSC Microprocessors

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2019, 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC).

Layout to Logic Defect Analysis for Hierarchical Test Generation

Raimund Ubar, Jaan Raik, Witold A. Pleskacz, 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

Mutation analysis with high-level decision diagrams

Raimund Ubar, Jaan Raik, Franco Fummi, 2010, 2010 11th Latin American Test Workshop.

Energy-Efficient Multi-fragment Markov Model Guided Online Model-Based Testing for MPSoC

Leonidas Tsiopoulos, Jaan Raik, Sven Nõmm, 2019 .

High-Level Decision Diagram Simulation for Diagnosis and Soft-Error Analysis

Jaan Raik, Maksim Jenihhin, Anton Chepurov, 2011 .

Extensible open-source framework for translating RTL VHDL IP cores to SystemC

Jaan Raik, Maksim Jenihhin, Syed Saif Abrar, 2013, 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Hierarchical identification of NBTI-critical gates in nanoscale logic

Fabian Vargas, Raimund Ubar, Jaan Raik, 2014, 2014 15th Latin American Test Workshop - LATW.

High-Level Decision Diagrams based coverage metrics for verification and test

Raimund Ubar, Jaan Raik, Uljana Reinsalu, 2009, 2009 10th Latin American Test Workshop.

Mixed hierarchical-functional fault models for targeting sequential cores

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2008, J. Syst. Archit..

BASTION: Board and SoC test instrumentation for ageing and no failure found

Jaan Raik, Hans G. Kerkhoff, Matteo Sonza Reorda, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Hardware Modeling for Design Verification and Debug

Jaan Raik, Maksim Jenihhin, Anton Tsepurov, 2013 .

Comprehensive Abstraction of VHDL RTL Cores to ESL SystemC. Register-siirde taseme VHDL kirjelduste kompleksne abstraheerimine süsteemitaseme SystemC mudeliteks

Jaan Raik, Maksim Jenihhin, 2016 .

A scalable model based RTL framework zamiaCAD for static analysis

Jaan Raik, Maksim Jenihhin, Rainer Dorsch, 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications

Jaan Raik, Massimo Violante, Siavoosh Payandeh Azad, 2018, 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

High-level design error diagnosis using backtrace on decision diagrams

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2010, NORCHIP 2010.

Application Specific True Critical Paths Identification in Sequential Circuits

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors

Dan Alexandrescu, Thomas Lange, Maksim Jenihhin, 2019, 2019 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits

Hideo Fujiwara, Raimund Ubar, Jaan Raik, 2011, 2011 Sixteenth IEEE European Test Symposium.

A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs

Said Hamdioui, Mottaqiallah Taouil, Guilherme Cardoso Medeiros, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Gate-level modelling of NBTI-induced delays under process variations

Fabian Vargas, Raimund Ubar, Jaan Raik, 2016, 2016 17th Latin-American Test Symposium (LATS).

Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks

Matteo Sonza Reorda, Said Hamdioui, Maksim Jenihhin, 2020, 2020 IEEE 38th VLSI Test Symposium (VTS).

An optimization framework for dynamic pipeline management in computing systems

Syed Rameez Naqvi, Tallha Akram, Kumar Yelamarthi, 2019, Comput. Electr. Eng..

An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements

Jaan Raik, Zainalabedin Navabi, Maksim Jenihhin, 2019, 2019 IEEE East-West Design & Test Symposium (EWDTS).

Hardware Modeling for Design Verification and Debug. Riistvara modelleerimine disaini verifitseerimise ja silumise jaoks

Jaan Raik, Maksim Jenihhin, 2013 .

An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architecture

Raimund Ubar, Zebo Peng, Gert Jervan, 2004 .

Software-Based Mitigation for Memory Address Decoder Aging

Jaan Raik, Said Hamdioui, Mottaqiallah Taouil, 2019, 2019 IEEE Latin American Test Symposium (LATS).

On the Combined Use of HLDDs and EFSMs for Functional ATPG

Raimund Ubar, Franco Fummi, Graziano Pravadelli, 2007 .

Hybrid BIST time minimization for core-based systems with STUMPS architecture

Petru Eles, Raimund Ubar, Zebo Peng, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDs

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2020, Microprocess. Microsystems.

Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors

Raimund Ubar, Maksim Jenihhin, Jaan Raik, 2020, 2020 23rd Euromicro Conference on Digital System Design (DSD).

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2019, 2019 IEEE European Test Symposium (ETS).

PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2009, J. Electron. Test..

Automated Design Error Localization in RTL Designs

Raimund Ubar, Jaan Raik, Heinz-Dietrich Wuttke, 2014, IEEE Design & Test.

Wafer-Level Die Re-Test Success Prediction Using Machine Learning

Peeter Ellervee, Maksim Jenihhin, Hardi Selg, 2020, 2020 IEEE Latin-American Test Symposium (LATS).

Multi-view modeling for MPSoC design aspects

Leonidas Tsiopoulos, Jaan Raik, Maksim Jenihhin, 2018, 2018 16th Biennial Baltic Electronics Conference (BEC).

Software-Level TMR Approach for On-Board Data Processing in Space Applications

Görschwin Fey, Jaan Raik, Thomas Hollstein, 2018, 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Timing-critical path analysis with structurally synthesized BDDs

Raimund Ubar, Jaan Raik, Vladimir Viies, 2018, 2018 7th Mediterranean Conference on Embedded Computing (MECO).

Understanding multidimensional verification: Where functional meets non-functional

Dan Alexandrescu, Jaan Raik, Tara Ghasempouri, 2019, Microprocess. Microsystems.

Hierarchical Timing-Critical Paths Analysis in Sequential Circuits

Raimund Ubar, Jaan Raik, Sergei Kostin, 2018, 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Designing Reliable Cyber-Physical Systems

Jaan Raik, Hans G. Kerkhoff, Sergei Devadze, 2018 .

Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints

Hideo Fujiwara, Anton Karputkin, Raimund Ubar, 2012, J. Electron. Test..

Towards Multidimensional Verification: Where Functional Meets Non-Functional

Jaan Raik, Tara Ghasempouri, Maksim Jenihhin, 2018, 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).

Automated design error debug using high-level decision diagrams and mutation operators

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2013, Microprocess. Microsystems.

Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation

Giovanni Squillero, Raimund Ubar, Jaan Raik, 2014, EvoApplications.

Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing

Jaan Raik, Maksim Jenihhin, Ahmet Cagri Bagbaba, 2019, 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).

Code Coverage Analysis using High-Level Decision Diagrams

Raimund Ubar, Jaan Raik, Peeter Ellervee, 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

On Test Generation for Microprocessors for Extended Class of Functional Faults

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2019, VLSI-SoC.

Modeling Microprocessor Faults on High-Level Decision Diagrams

Raimund Ubar, Jaan Raik, Heinz-Dietrich Wuttke, 2008 .

Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis

Jaan Raik, Massimo Violante, Siavoosh Payandeh Azad, 2018, 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

On NBTI-induced Aging Analysis in IEEE 1687 Reconfigurable Scan Networks

Giovanni Squillero, Maksim Jenihhin, Aleksa Damljanovic, 2019, 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC).

PSL assertion checkers synthesis with ASM based HLS tool ABELITE

Jaan Raik, Samary Baranov, Maksim Jenihhin, 2012, 2012 13th Latin American Test Workshop (LATW).

New categories of Safe Faults in a processor-based Embedded System

Raimund Ubar, Jaan Raik, Matteo Sonza Reorda, 2019, 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Abstraction of clock interface for conversion of RTL VHDL to SystemC

Jaan Raik, Maksim Jenihhin, Syed Saif Abrar, 2014, 2014 IEEE International Advance Computing Conference (IACC).

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

Fabian Vargas, Giovanni Squillero, Raimund Ubar, 2016, J. Electron. Test..

Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices pdf

Kolin Paul, Roel Maes, Maksim Jenihhin, 2020, ArXiv.

An approach for PSL assertion coverage analysis with high-level decision diagrams

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2010, 2010 East-West Design & Test Symposium (EWDTS).

PASCAL: Timing SCA Resistant Design and Verification Flow

Jaan Raik, Kolin Paul, Maksim Jenihhin, 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS).

FSMD RTL design manipulation for clock interface abstraction

Jaan Raik, Maksim Jenihhin, Syed Saif Abrar, 2015, 2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI).

RESCUE: Cross-Sectoral PhD Training Concept for Interdependent Reliability, Security and Quality

Heinrich Theodor Vierhaus, Matteo Sonza Reorda, Maksim Jenihhin, 2018, 2018 12th European Workshop on Microelectronics Education (EWME).

Test Time Minimization for Hybrid BIST of Core-Based Systems

Petru Eles, Raimund Ubar, Zebo Peng, 2003, 2003 Test Symposium.

Challenges of Reliability Assessment and Enhancement in Autonomous Systems

Dan Alexandrescu, Matteo Sonza Reorda, Maksim Jenihhin, 2019, 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

On the Reuse of TLM Mutation Analysis at RTL

Raimund Ubar, Jaan Raik, Franco Fummi, 2012, J. Electron. Test..

Test Time Minimization for Hybrid BIST with Test Pattern Broadcasting

Raimund Ubar, Zebo Peng, Gert Jervan, 2003 .

Combining dynamic slicing and mutation operators for ESL correction

Raimund Ubar, Jaan Raik, Franco Fummi, 2012, 2012 17th IEEE European Test Symposium (ETS).

Performance analysis of cosimulating processor core in VHDL and SystemC

Jaan Raik, Maksim Jenihhin, Syed Saif Abrar, 2013, 2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI).

Hybrid BIST optimization for core-based systems with test pattern broadcasting

Raimund Ubar, Maksim Jenihhin, 2004, Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications.

Designing reliable cyber-physical systems overview associated to the special session at FDL'16

Yong Zhao, Görschwin Fey, Jaan Raik, 2016, 2016 Forum on Specification and Design Languages (FDL).

Multi-Fragment Markov Model Guided Online Test Generation for MPSoC

Leonidas Tsiopoulos, Jaan Raik, Jüri Vain, 2017, ICTERI.

High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2020, J. Electron. Test..

Representing Gate-Level SET Faults by Multiple SEU Faults at RTL

Raimund Ubar, Maksim Jenihhin, Ahmet Cagri Bagbaba, 2020, 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Fast identification of true critical paths in sequential circuits

Raimund Ubar, Jaan Raik, Sergei Kostin, 2018, Microelectron. Reliab..

Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG

Fabian Vargas, Giovanni Squillero, Jaan Raik, 2015, 2015 16th Latin-American Test Symposium (LATS).

Efficient Fault Injection based on Dynamic HDL Slicing Technique

Jaan Raik, Maksim Jenihhin, Ahmet Cagri Bagbaba, 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Universal mitigation of NBTI-induced aging by design randomization

Zainalabedin Navabi, Maksim Jenihhin, Somayeh Sadeghi Kohan, 2016, 2016 IEEE East-West Design & Test Symposium (EWDTS).

SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores

Jaan Raik, Maksim Jenihhin, Syed Saif Abrar, 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic

Fabian Vargas, Raimund Ubar, Jaan Raik, 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Mutation analysis for SystemC designs at TLM

Raimund Ubar, Jaan Raik, Franco Fummi, 2011, 2011 12th Latin American Test Workshop (LATW).

Dependability evaluation in fault-tolerant systems with high-level decision diagrams

Raimund Ubar, Jaan Raik, Peeter Ellervee, 2007 .

Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs

Giovanni Squillero, Raimund Ubar, Jaan Raik, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

Assessment of diagnostic test for automated bug localization

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2013, 2013 14th Latin American Test Workshop - LATW.

Constraint-based test pattern generation at the Register-Transfer Level

Raimund Ubar, Jaan Raik, Anna Krivenko, 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance

Raimund Ubar, Jaan Raik, Sergei Devadze, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications

Dan Alexandrescu, Thomas Lange, Maksim Jenihhin, 2019, 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).

A scalable technique to identify true critical paths in sequential circuits

Raimund Ubar, Jaan Raik, Sergei Kostin, 2017, 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Identifying NBTI-Critical Paths in Nanoscale Logic

Fabian Vargas, Raimund Ubar, Jaan Raik, 2013, 2013 Euromicro Conference on Digital System Design.

E-Learning Environment for WEB-Based Study of Testing

Raimund Ubar, Sergei Kostin, Heinz-Dietrich Wuttke, 2010 .

Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects

Dan Alexandrescu, Thomas Lange, Maksim Jenihhin, 2020, 2020 9th Mediterranean Conference on Embedded Computing (MECO).

Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2012, 2012 13th Latin American Test Workshop (LATW).

Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC

Raimund Ubar, Jaan Raik, Witold A. Pleskacz, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

EEG Analyzer prototype based on FPGA

Maksim Gorev, Peeter Ellervee, Hiie Hinrikus, 2011, 2011 7th International Symposium on Image and Signal Processing and Analysis (ISPA).

True Path Tracing in Structurally Synthesized BDDs for Testability Analysis of Digital Circuits

Raimund Ubar, Maksim Jenihhin, Lembit Jürimägi, 2019, 2019 22nd Euromicro Conference on Digital System Design (DSD).

Localization of Bugs in Processor Designs Using zamiaCAD Framework

Jaan Raik, Heinz-Dietrich Wuttke, Maksim Jenihhin, 2012, 2012 13th International Workshop on Microprocessor Test and Verification (MTV).

RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems

Dan Alexandrescu, Heinrich Theodor Vierhaus, Zoya Dyka, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Test Time Minimization for Hybrid BIST of Core-Based Systems

Petru Eles, Raimund Ubar, Zebo Peng, 2006, Journal of Computer Science and Technology.

Application of high-level decision diagrams for simulation-based verification tasks

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2010 .

Mixed-level identification of fault redundancy in microprocessors

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2019, 2019 IEEE Latin American Test Symposium (LATS).

Edge-to-Fog Collaborative Computing in a Swarm of Drones

Muhammad Mahtab Alam, Yannick Le Moullec, Maksim Jenihhin, 2021, MEDI Workshops.

Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2021, 2021 24th Euromicro Conference on Digital System Design (DSD).

A Methodology for Automated Mining of Compact and Accurate Assertion Sets

Jaan Raik, Tara Ghasempouri, Gert Jervan, 2021, 2021 IEEE Nordic Circuits and Systems Conference (NorCAS).

Gate-Level Graph Representation Learning: A Step Towards the Improved Stuck-at Faults Analysis

Dan Alexandrescu, Maksim Jenihhin, Maximilien Glorieux, 2021, 2021 22nd International Symposium on Quality Electronic Design (ISQED).

Modeling Soft-Error Reliability Under Variability

Dan Alexandrescu, Said Hamdioui, Guilherme Cardoso Medeiros, 2021, 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Fast and Fair Computation Offloading Management in a Swarm of Drones Using a Rating-Based Federated Learning Approach

Muhammad Mahtab Alam, Yannick Le Moullec, Maksim Jenihhin, 2021, IEEE Access.

Assertion Checking with PSL and High-Level Decision Diagrams

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2007 .

FPGA-Based Implementation of EEG Analyzer

Maksim Gorev, Peeter Ellervee, Maksim Jenihhin, 2010 .

BELAS Registration Form 2 nd Biannual European - Latin American Summer School on Design, Test and Reliability

Jaan Raik, Jose Lipovetzky, Maksim Jenihhin, 2014 .