Davide Pandini

发表

Influence of the IEC 61967 Test Board on IC Electromagnetic Emissions

Yamarita Villavicencio, Francesco Musolino, Franco Fiori, 2009, 2009 20th International Zurich Symposium on Electromagnetic Compatibility.

A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells

Davide Pandini, Fabrizio Ferrandi, Christian Pilato, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

Clock Distribution Techniques for Low-EMI Design

Davide Pandini, Guido A. Repetto, Vincenzo Sinisi, 2007, PATMOS.

A design methodology for the automatic sizing of standard-cell libraries

Davide Pandini, Fabrizio Ferrandi, Christian Pilato, 2011, GLSVLSI '11.

Crosstalk aware static timing analysis: a two step approach

Primo Scandolara, Davide Pandini, Bruno Franzini, 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

Why we need statistical static timing analysis

Davide Pandini, Cristiano Forzan, 2007, 2007 25th International Conference on Computer Design.

EMC-aware design on a microcontroller for automotive applications

Yamarita Villavicencio, Davide Pandini, Mario Rotigni, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Session details: Modeling tech. impact

Davide Pandini, 2007, DAC '07.

Understanding and addressing the impact of wiring congestion during technology mapping

Davide Pandini, Andrzej J. Strojwas, Lawrence T. Pileggi, 2002, ISPD '02.

Clock-tree synthesis for low-EMI design

Davide Pandini, Guido A. Repetto, Vincenzo Sinisi, 2009, J. Embed. Comput..

Power Supply Selective Mapping for Accurate Timing Analysis

Mariagrazia Graziano, Davide Pandini, Cristiano Forzan, 2006, J. Low Power Electron..

Statistical static timing analysis: A survey

Davide Pandini, Cristiano Forzan, C. Forzan, 2009, Integr..

Design methodologies and architecture solutions for high-performance interconnects

Davide Pandini, Cristiano Forzan, Livio Baldi, 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

Reduced order macromodel of coupled interconnects for timing and functional verification of sub-half-micron IC designs

Carlo Guardiani, Primo Scandolara, Davide Pandini, 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

Improving Electro-Magnetic Interference of Embedded Systems Through Jittered-Delay Desynchronization

Luciano Lavagno, Davide Pandini, Fabio Campi, 2010, J. Low Power Electron..

Design methodology for low-power embedded microprocessors

Davide Pandini, Fabio Campi, Valentino Liberali, 2013, 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Optimum CMOS stack generation with analog constraints

Davide Pandini, Enrico Malavasi, E. Malavasi, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Automatic generation of transistor stacks for CMOS analog layout

Davide Pandini, Enrico Malavasi, Valentino Liberali, 1993, 1993 IEEE International Symposium on Circuits and Systems.

A complete methodology for an accurate static noise analysis

Davide Pandini, Cristiano Forzan, 2005, GLSVLSI '05.

A comparison between mask- and field-programmable routing structures on industrial FPGA architectures

Davide Pandini, Luca Macchiarulo, Consolato F. Caccamo, 2004, GLSVLSI '04.

Spectral Analysis of the On-Chip Waveforms to Generate Guidelines for EMC-Aware Design

Davide Pandini, Guido A. Repetto, 2006, PATMOS.

A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis

Davide Pandini, Fabrizio Ferrandi, Donatella Sciuto, 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

Robust Design-for-Productization Practices for High Quality Automotive Products

Davide Pandini, Paolo Bernardi, Davide Appello, 2008, 2008 IEEE International Test Conference.

Modeling the non-linear behavior of library cells for an accurate static noise analysis

Davide Pandini, Cristiano Forzan, 2005, Design, Automation and Test in Europe.

Exploiting body biasing for leakage reduction: A case study

Davide Pandini, Davide Rossi, Fabio Campi, 2013, 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Evaluating Static CMOS Complex Cells in Technology Mapping

Davide Pandini, Fabrizio Ferrandi, Christian Pilato, 2011, ARCS Workshops.

Bounding the efforts on congestion optimization for physical synthesis

Davide Pandini, Andrzej J. Strojwas, Lawrence T. Pileggi, 2003, GLSVLSI '03.

Evaluating the impact of substrate on power integrity in industrial microcontrollers

Davide Pandini, Valentino Liberali, Patrice Joubert Doriol, 2013, 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Computing and design for software and silicon manufacturing

Davide Pandini, Alessandro Cremonesi, Giuseppe Desoli, 2007, 2007 IFIP International Conference on Very Large Scale Integration.

Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies

Davide Pandini, 2007, PATMOS.

Global and local congestion optimization in technology mapping

Davide Pandini, Andrzej J. Strojwas, Lawrence T. Pileggi, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies

Davide Pandini, 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

Optimum stacked layout for analog CMOS ICs

Davide Pandini, Valentino Liberali, E. Malavasi, 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

Congestion-aware logic synthesis

Davide Pandini, Andrzej J. Strojwas, Lawrence T. Pileggi, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Simultaneous Placement and Module Optimization of Analog IC's

Alberto L. Sangiovanni-Vincentelli, Davide Pandini, Edoardo Charbon, 1994, 31st Design Automation Conference.

SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels

Davide Pandini, Fabrizio Ferrandi, Renato P. Ribas, 2011, ARCS Workshops.

Evaluating the impact of substrate noise on conducted EMI in automotive microcontrollers

Davide Pandini, Valentino Liberali, Patrice Joubert Doriol, 2013, 2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo).

Electromagnetic Interference Reduction on an Automotive Microcontroller

Davide Pandini, Mario Rotigni, Cristiano Forzan, 2009, DAC 2009.

CMOS Layout Module Generation with Matching Constraints

Davide Pandini, Enrico Malavasi, 1993 .

Power Supply Selective Mapping for Accurate Timing Analysis

Mariagrazia Graziano, Davide Pandini, Cristiano Forzan, 2005, PATMOS.

A Fully-Automated Desynchronization Flow for Synchronous Circuits

Luciano Lavagno, Davide Pandini, Christos P. Sotiriou, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Maximization of layout printability/manufacturability by extreme layout regularity

Davide Pandini, Andrzej J. Strojwas, Tejas Jhaveri, 2007 .

Advanced Modeling Techniques for System-level Power Integrity Analysis

Davide Pandini, Mario Rotigni, Cristiano Forzan, 2009 .

An ultra-low energy asynchronous processor for wireless sensor networks

Luca Necchi, Luciano Lavagno, Laura Vanzago, 2006, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06).

Variability in Advanced Nanometer Technologies: Challenges and Solutions

Davide Pandini, 2009, PATMOS.

Including Power Supply Variations into Static Timing Analysis: Methodology and Flow

Mariagrazia Graziano, Davide Pandini, Cristiano Forzan, 2005, Proceedings 2005 IEEE International SOC Conference.

Advanced modeling techniques for system-level power integrity and EMC analysis

Yamarita Villavicencio, Davide Pandini, Mario Rotigni, 2009, 2009 European Microelectronics and Packaging Conference.