Ardavan Pedram

发表

Campfire: Compressible, Regularization-Free, Structured Sparse Training for Hardware Accelerators pdf

Kais Kudrolli, Noah Gamboa, Anand Dhoot, 2020, ArXiv.

A Highly Efficient Multicore Floating-Point FFT Architecture Based on Hybrid Linear Algebra/FFT Cores

Andreas Gerstlauer, John D. McCalpin, Ardavan Pedram, 2014, J. Signal Process. Syst..

Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era

Stephen Richardson, Ardavan Pedram, Shahar Kvatinsky, 2016, IEEE Design & Test.

An Efficient Parallel Architecture for Matrix Computations

Masoud Daneshtalab, Sied Mehdi Fakhraie, Ardavan Pedram, 2006, 2006 NORCHIP.

Plasticine: A reconfigurable architecture for parallel patterns

Kunle Olukotun, Christoforos E. Kozyrakis, Yaqi Zhang, 2017, 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA).

Spatial: a language and compiler for application accelerators

Kunle Olukotun, Christoforos E. Kozyrakis, Yaqi Zhang, 2018, PLDI.

Improving energy efficiency of DRAM by exploiting half page row access

Mark Horowitz, Stephen Richardson, Ardavan Pedram, 2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

On the Efficiency of Register File versus Broadcast Interconnect for Collective Communications in Data-Parallel Hardware Accelerators

Robert A. van de Geijn, Andreas Gerstlauer, Ardavan Pedram, 2012, 2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing.

Simulator calibration for accelerator-rich architecture studies

Andreas Gerstlauer, Lizy Kurian John, Ardavan Pedram, 2016, 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS).

A Systematic Approach to Blocking Convolutional Neural Networks pdf

Xuan Yang, Stephen Richardson, Jonathan Ragan-Kelley, 2016, ArXiv.

Floating Point Architecture Extensions for Optimized Matrix Factorization

Robert A. van de Geijn, Andreas Gerstlauer, Ardavan Pedram, 2013, 2013 IEEE 21st Symposium on Computer Arithmetic.

Deep compression and EIE: Efficient inference engine on compressed deep neural network

Song Han, Mark Horowitz, Xingyu Liu, 2016, 2016 IEEE Hot Chips 28 Symposium (HCS).

Evaluating programmable architectures for imaging and vision applications

Mark Horowitz, Stephen Richardson, Ardavan Pedram, 2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

A high-performance, low-power linear algebra core

Robert A. van de Geijn, Andreas Gerstlauer, Ardavan Pedram, 2011, ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors.

Plasticine: A Reconfigurable Accelerator for Parallel Patterns

Kunle Olukotun, Christoforos E. Kozyrakis, Yaqi Zhang, 2018, IEEE Micro.

A Linear Algebra Core Design for Efficient Level-3 BLAS

Robert A. van de Geijn, Andreas Gerstlauer, Nam Sung Kim, 2012, 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors.

Transforming a linear algebra core to an FFT accelerator

Andreas Gerstlauer, John D. McCalpin, Ardavan Pedram, 2013, 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors.

EIE: Efficient Inference Engine on Compressed Deep Neural Network

Song Han, William J. Dally, Mark Horowitz, 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

Algorithm, Architecture, and Floating-Point Unit Codesign of a Matrix Factorization Accelerator

Robert A. van de Geijn, Andreas Gerstlauer, Ardavan Pedram, 2014, IEEE Transactions on Computers.

Codesign Tradeoffs for High-Performance, Low-Power Linear Algebra Architectures

Robert A. van de Geijn, Andreas Gerstlauer, Ardavan Pedram, 2012, IEEE Transactions on Computers.

Algorithm/Architecture Codesign of Low Power and High Performance Linear Algebra Compute Fabrics

Ardavan Pedram, A. Pedram, 2013, 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum.

Modeling Cache Effects at the Transaction Level

Andreas Gerstlauer, Ardavan Pedram, David Craven, 2009, IESS.

CATERPILLAR: Coarse Grain Reconfigurable Architecture for accelerating the training of Deep Neural Networks

Ardavan Pedram, Yuanfang Li, A. Pedram, 2017, 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

Griffin: Rethinking Sparse Optimization for Deep Learning Architectures

Ardavan Pedram, Ling Li, Hamzah Abdel-Aziz, 2021, 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

Rethinking Floating Point Overheads for Mixed Precision DNN Accelerators pdf

Ardavan Pedram, Hamzah Abdel-Aziz, Ali Shafiee, 2021, MLSys.

Design Space Exploration of Sparse Accelerators for Deep Neural Networks pdf

Ardavan Pedram, Ling Li, Hamzah Abdel-Aziz, 2021, ArXiv.

Towards a High-Performance , Low-Power Linear Algebra Processor

Andreas Gerstlauer, Ardavan Pedram, R. V. D. Geijn, 2010 .