Pawel Chodowiec

发表

IPsec-Protected Transport of HDTV over IP

Colin Perkins, Kris Gaj, Peter Bellows, 2003 .

Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining

Kris Gaj, Pawel Chodowiec, Po Khuon, 2001, FPGA '01.

InvMixColumn decomposition and multilevel resource sharing in AES implementations

Milos Drutarovský, Viktor Fischer, Pawel Chodowiec, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Implementation of the Twofish Cipher Using FPGA Devices

Kris Gaj, Pawel Chodowiec, 1999 .

Very Compact FPGA Implementation of the AES Algorithm

Kris Gaj, Pawel Chodowiec, K. Gaj, 2003, CHES.

Hardware performance of the AES finalists-survey and analysis of results

Kris Gaj, Pawel Chodowiec, K. Gaj, 2000 .

IPsec-Protected Transport of HDTV over IP

Colin Perkins, Kris Gaj, Peter Bellows, 2003, FPL.

FPGA and ASIC Implementations of AES

Kris Gaj, Pawel Chodowiec, K. Gaj, 2009, Cryptographic Engineering.

Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware

Kris Gaj, Pawel Chodowiec, K. Gaj, 2000, AES Candidate Conference.

Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board

Kris Gaj, Peter Bellows, Brian Schott, 2001, ISC.

Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard Using Field Programmable Gate Arrays

Kris Gaj, Pawel Chodowiec, 2001, CT-RSA.

Hardware implementation of IPSec cryptographic transformations

Pawel Chodowiec, Issam Andoni, Jacek Radzikowski, 2001 .