J.D. Bruguera

Floating-point fused multiply-add with reduced latency

T. Lang, J.D. Bruguera, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Representation of unit range numbers

J.D. Bruguera, T. Lang, 2005, Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005..