Abhijit Jas

发表

Achieving high encoding efficiency with partial dynamic LFSR reseeding

Nur A. Touba, C. V. Krishna, Abhijit Jas, 2004, TODE.

Nur A. Touba, C. V. Krishna, Abhijit Jas, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Virtual scan chains: a means for reducing scan length in cores

Nur A. Touba, Bahram Pouya, Abhijit Jas, 2000, Proceedings 18th IEEE VLSI Test Symposium.

Analysis of Specified Bit Handling Capability of Combinational Expander Networks

Srinivas Patil, Abhijit Jas, S. Patil, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

Hybrid BIST based on weighted pseudo-random testing: a new test resource partitioning scheme

Nur A. Touba, C. V. Krishna, Abhijit Jas, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

Test vector decompression via cyclical scan chains and its application to testing core-based designs

Nur A. Touba, Abhijit Jas, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Configuration self-test in FPGA-based reconfigurable systems

Nur A. Touba, Abhijit Jas, W. Quddus, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

A low-cost concurrent error detection technique for processor control logic

Jacob A. Abraham, Srinivas Patil, Ramtilak Vemu, 2008, 2008 Design, Automation and Test in Europe.

RT-Level Deviation-Based Grading of Functional Test Sequences

Krishnendu Chakrabarty, Chandra Tirumurti, Srinivas Patil, 2009, 2009 27th IEEE VLSI Test Symposium.

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

Nur A. Touba, Abhijit Jas, 2002, J. Electron. Test..

An Approach to Minimizing Functional Constraints

Sreejit Chakravarty, Yi-Shing Chang, Abhijit Jas, 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Using an embedded processor for efficient deterministic testing of systems-on-a-chip

Nur A. Touba, Abhijit Jas, 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

Scan vector compression/decompression using statistical coding

Nur A. Touba, Abhijit Jas, Jayabrata Ghosh-Dastidar, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

FPGA-based hardware acceleration for Boolean satisfiability

Srinivas Patil, Sunil P. Khatri, Abhijit Jas, 2009, TODE.

Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes

Avijit Dutta, Abhijit Jas, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller

Michail Maniatakos, Yiorgos Makris, Chandra Tirumurti, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

A Methodology for Handling Complex Functional Constraints for Large Industrial Designs

Sreejit Chakravarty, Yi-Shing Chang, Abhijit Jas, 2008, J. Electron. Test..

Impact analysis of performance faults in modern microprocessors

Michail Maniatakos, Yiorgos Makris, Chandra Tirumurti, 2009, 2009 IEEE International Conference on Computer Design.

Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller

Michail Maniatakos, Yiorgos Makris, Chandra Tirumurti, 2011, IEEE Transactions on Computers.

Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller

Michail Maniatakos, Yiorgos Makris, Chandra Tirumurti, 2009, 2009 27th IEEE VLSI Test Symposium.

Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors

Cecilia Metra, Martin Omaña, Daniele Rossi, 2010, CF '10.

Functional Test-Sequence Grading at Register-Transfer Level

Krishnendu Chakrabarty, Chandra Tirumurti, Srinivas Patil, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic

Cecilia Metra, Martin Omaña, Daniele Rossi, 2008, 2008 13th European Test Symposium.

Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering

Abhijit Jas, Hai Zhou, Kip Killpack, 2008, ASP-DAC 2008.

On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors

Michail Maniatakos, Yiorgos Makris, Abhijit Jas, 2008, 2008 IEEE International Test Conference.

An efficient test vector compression scheme using selective Huffman coding

Nur A. Touba, Abhijit Jas, Jayabrata Ghosh-Dastidar, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor

Michail Maniatakos, Yiorgos Makris, Chandra Tirumurti, 2011, IEEE Transactions on Computers.

An embedded core DFT scheme to obtain highly compressed test sets

Nur A. Touba, Kartik Mohanram, Abhijit Jas, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering

Hai Zhou, Chandramouli V. Kashyap, Abhijit Jas, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

AVF Analysis Acceleration via Hierarchical Fault Pruning

Michail Maniatakos, Yiorgos Makris, Chandra Tirumurti, 2011, 2011 Sixteenth IEEE European Test Symposium.

Test vector encoding using partial LFSR reseeding

Nur A. Touba, C. V. Krishna, Abhijit Jas, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Test data compression technique for embedded cores using virtual scan chains

Nur A. Touba, Bahram Pouya, Abhijit Jas, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder

Cecilia Metra, Martin Omaña, Daniele Rossi, 2013, J. Electron. Test..