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Impact of parasitic resistance and silicon layer thickness scaling for strained-silicon MOSFETs on relaxed Si/sub 1-x/Ge/sub x/ virtual substrate

N. Nagashima, K. Ohuchi, H. Ishiuchi, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Issues and optimization of millisecond anneal process for 45 nm node and beyond

K. Ohuchi, H. Ishiuchi, N. Aoki, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..