Sachin S. Sapatnekar

发表

Pingqiang Zhou, Sachin S. Sapatnekar, S. Sapatnekar, 2015 .

Feasible region approximation using convex polytopes

Sung-Mo Kang, Sachin S. Sapatnekar, Pravin M. Vaidya, 1993, 1993 IEEE International Symposium on Circuits and Systems.

The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk)

Sachin S. Sapatnekar, Ramesh Harjani, Tonmoy Dhar, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Process and Reliability Sensors for Nanoscale CMOS

Sachin S. Sapatnekar, John Keane, Chris H. Kim, 2012, IEEE Design & Test of Computers.

Circuit-aware on-chip inductance extraction

Sachin S. Sapatnekar, Haitian Hu, 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

Probability-driven routing in a datapath environment

Sachin S. Sapatnekar, Suresh Raman, Charles J. Alpert, 2002, Integr..

Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing

Sachin S. Sapatnekar, Tianpei Zhang, S. Sapatnekar, 2007, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

Power vs. delay in gate sizing: conflicting objectives?

Weitong Chuang, Sachin S. Sapatnekar, 1995, ICCAD.

Predicting electromigration mortality under temperature and product lifetime specifications

Sachin S. Sapatnekar, Vivek Mishra, S. Sapatnekar, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Minimum area retiming with equivalent initial states

Sachin S. Sapatnekar, Naresh Maheshwari, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Enabling improved power management in multicore processors through clustered DVFS

Antonia Zhai, Sachin S. Sapatnekar, T. Kolpe, 2010, 2011 Design, Automation & Test in Europe.

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Keshab K. Parhi, Sachin S. Sapatnekar, Martin Kuhlmann, 1999 .

Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization

Sachin S. Sapatnekar, Gracieli Posser, Ricardo Reis, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Designing Digital Computer Systems with Verilog: Verification

Sachin S. Sapatnekar, David J. Lilja, D. Lilja, 2004 .

A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations

Sachin S. Sapatnekar, Jaskirat Singh, S. Sapatnekar, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Thermally Aware Design

Sachin S. Sapatnekar, Yong Zhan, Sanjay V. Kumar, 2008, Found. Trends Electron. Des. Autom..

RTL Synthesis: From Logic Synthesis to Automatic Pipelining

Sachin S. Sapatnekar, Jordi Cortadella, Michael Kishinevsky, 2015, Proceedings of the IEEE.

Tutorial II: Variability and Its Impact on Design

Sachin S. Sapatnekar, Keith A. Bowman, Michael Orshansky, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Fast algorithms for retiming large digital circuits

Sachin S. Sapatnekar, Naresh Maheshwari, 1998 .

Dynamic Approximation of JPEG Hardware

Sachin S. Sapatnekar, Jiang Hu, Farhana Sharmin Snigdha, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization

Sachin S. Sapatnekar, John P. Fishburn, Harsha Sathyamurthy, 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Message from the Technical Program Chairs

Sachin S. Sapatnekar, Alok Jain, 2013, VLSID 2013.

Cost-quality trade-offs of approximate memory repair mechanisms for image data

Sachin S. Sapatnekar, David J. Lilja, Qianqian Fan, 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

Efficient retiming of large circuits

Sachin S. Sapatnekar, Naresh Maheshwari, 1998, IEEE Trans. Very Large Scale Integr. Syst..

The impact of shallow trench isolation effects on circuit performance

Sachin S. Sapatnekar, Sravan K. Marella, S. Sapatnekar, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Gate Oxide Leakage and Delay Tradeoffs for

Dennis Sylvester, Sachin S. Sapatnekar, Anup Kumar Sultania, 2005 .

Moment-based techniques for RLC clock tree construction

Sachin S. Sapatnekar, D. Lehther, 1998 .

A DNA Read Alignment Accelerator Based on Computational RAM

Sachin S. Sapatnekar, Ulya R. Karpuzcu, Meisam Razaviyayn, 2020, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.

Congestion-aware topology optimization of structured power/ground networks

Sachin S. Sapatnekar, Jaskirat Singh, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A convex optimization approach to transistor sizing for CMOS circuits

Sachin S. Sapatnekar, Pravin M. Vaidya, Vasant B. Rao, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

Book Reviews: Plumbing the Depths of Leakage

Sachin S. Sapatnekar, 2006, IEEE Design & Test of Computers.

MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification pdf

Sachin S. Sapatnekar, Brucek Khailany, Ben Keller, 2020, ArXiv.

Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property

Jie Gu, Sachin S. Sapatnekar, John Keane, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Buffered Steiner trees for difficult instances

Sachin S. Sapatnekar, Charles J. Alpert, Andrew B. Kahng, 2002 .

A Machine Learning Accelerator In-Memory for Energy Harvesting pdf

Sachin S. Sapatnekar, Zhengyang Zhao, Ulya R. Karpuzcu, 2019, ArXiv.

A practical algorithm for retiming level-clocked circuits

Sachin S. Sapatnekar, Naresh Maheshwari, 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

A precorrected-FFT method for simulating on-chip inductance

Rajendran Panda, Min Zhao, Sachin S. Sapatnekar, 2002, ICCAD 2002.

Scalable methods for the analysis and optimization of gate oxide breakdown

Sachin S. Sapatnekar, Jianxin Fang, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Spiking Neural Networks in Spintronic Computational RAM pdf

Sachin S. Sapatnekar, Ulya R. Karpuzcu, Thomas J. Peterson, 2020, ACM Trans. Archit. Code Optim..

Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliability

Sachin S. Sapatnekar, Jianxin Fang, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Stochastic Preconditioning for Diagonally Dominant Matrices

Sachin S. Sapatnekar, Haifeng Qian, S. Sapatnekar, 2008, SIAM J. Sci. Comput..

Distributed On-Chip Switched-Capacitor DC–DC Converters Supporting DVFS in Multicore Systems

Pingqiang Zhou, Sachin S. Sapatnekar, Chris H. Kim, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An Analytical Model for Negative Bias Temperature Instability

Sachin S. Sapatnekar, Chris H. Kim, Sanjay V. Kumar, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

A chip-level electrostatic discharge simulation strategy

Sani R. Nassif, Sachin S. Sapatnekar, Haifeng Qian, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

A framework for block-based timing sensitivity analysis

Sachin S. Sapatnekar, Chandramouli V. Kashyap, Sanjay V. Kumar, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Editorial

Sachin S. Sapatnekar, Sachin S. Sapatnekar, 2010, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

The impact of electromigration in copper interconnects on power grid integrity

Sachin S. Sapatnekar, Vivek Mishra, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Algorithmic behavioral modeling

Sachin S. Sapatnekar, David J. Lilja, D. Lilja, 2004 .

A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area

Weitong Chuang, Ibrahim N. Hajj, Sachin S. Sapatnekar, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

Combined transistor sizing with buffer insertion for timing optimization

Sachin S. Sapatnekar, Juho Kim, Yanbin Jiang, 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

CATALYST: Planning layer directives for effective design closure

Shiyan Hu, Sachin S. Sapatnekar, Charles J. Alpert, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Tutorial 3: Optimization strategies for physical synthesis and timing closure

Sachin S. Sapatnekar, Charles J. Alpert, S. Raje, 2001, ICCAD 2001.

Error control algorithms and architectures for reliable dsp systems

Keshab K. Parhi, Sachin S. Sapatnekar, Renfei Liu, 2010 .

A timing-constrained simultaneous global routing algorithm

Sachin S. Sapatnekar, Jiang Hu, S. Sapatnekar, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Variability and Statistical Design

Sachin S. Sapatnekar, 2008, IPSJ Trans. Syst. LSI Des. Methodol..

Gate oxide leakage and delay tradeoffs for dual-T/sub ox/ circuits

Dennis Sylvester, Sachin S. Sapatnekar, Anup Kumar Sultania, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Optimized pin assignment for lower routing congestion after floorplanning phase

Sachin S. Sapatnekar, Tianpei Zhang, S. Sapatnekar, 2002, SLIP '02.

Stack Sizing for Optimal Current Drivability in Subthreshold Circuits

Sachin S. Sapatnekar, John Keane, Chris H. Kim, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Incremental power network analysis using backward random walks

Sachin S. Sapatnekar, Baktash Boghrati, 2012, 17th Asia and South Pacific Design Automation Conference.

Non-Hanan Optimization for Global VLSI Interconnect

Sachin S. Sapatnekar, Jiang Hu, S. Sapatnekar, 2001 .

Graceful Degradation of Low-Criticality Tasks in Multiprocessor Dual-Criticality Systems

Lin Huang, Sachin S. Sapatnekar, Jiang Hu, 2018, RTNS.

Convexity-based algorithms for design centering

Sachin S. Sapatnekar, Pravin M. Vaidya, Steve M. Kang, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning of CNN Computations on Cloud-Connected Mobile Clients

Sachin S. Sapatnekar, Farhana Sharmin Snigdha, Susmita Dey Manasi, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Temperature-Aware Placement for SOCs High and uneven temperatures can be avoided when appropriate thermal modeling and simulation are incorporated in placement algorithms for components and interconnections in systems-on-chip.

Sachin S. Sapatnekar, Haifeng Qian, Jeng-Liang Tsai, 2006 .

Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques

Sachin S. Sapatnekar, Andrew B. Kahng, Uday Mallappa, 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model

Sachin S. Sapatnekar, Jiang Hu, S. Sapatnekar, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A method for correcting the functionality of a wire-pipelined circuit

Sachin S. Sapatnekar, Vidyasagar Nookala, S. Sapatnekar, 2004, Proceedings. 41st Design Automation Conference, 2004..

Filtered Audio Clips from Approximate FIR Filters Designed Using the SABER Algorithm

Sachin S. Sapatnekar, Jiang Hu, Deepashree Sengupta, 2017 .

Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems

Antonia Zhai, Pingqiang Zhou, Sachin S. Sapatnekar, 2012, ISLPED '12.

Table look-up based compact modeling for on-chip interconnect timing and noise analysis

Rajendran Panda, David Blaauw, Min Zhao, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Adaptive techniques for overcoming performance degradation due to aging in digital circuits

Sachin S. Sapatnekar, Chris H. Kim, Sanjay V. Kumar, 2009, 2009 Asia and South Pacific Design Automation Conference.

Partition-based algorithm for power grid design using locality

Sachin S. Sapatnekar, Jaskirat Singh, S. Sapatnekar, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Optimal design of JPEG hardware under the approximate computing paradigm

Sachin S. Sapatnekar, Jiang Hu, Deepashree Sengupta, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Fast Stochastic Analysis of Electromigration in Power Distribution Networks

Sachin S. Sapatnekar, Vivek Mishra, Palkesh Jain, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A general model for performance optimization of sequential systems

Sachin S. Sapatnekar, Jordi Cortadella, Michael Kishinevsky, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Stress-Induced Performance Shifts in 3D DRAMs

Sachin S. Sapatnekar, Tengtao Li, S. Sapatnekar, 2019, ACM Trans. Design Autom. Electr. Syst..

On the selection of on-chip inductors for the optimal VCO design

Sachin S. Sapatnekar, Ramesh Harjani, Yong Zhan, 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

Statistical Timing Analysis

Sachin S. Sapatnekar, S. Sapatnekar, 2016, Encyclopedia of Algorithms.

A progressive-ILP based routing algorithm for cross-referencing biochips

Yao-Wen Chang, Chia-Lin Yang, Sachin S. Sapatnekar, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model

Sachin S. Sapatnekar, Jiang Hu, S. Sapatnekar, 1999, ISPD '99.

INVITED: Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project

Andrew B. Kahng, Mateus Fogaça, Sachin S. Sapatnekar, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Control synthesis and delay sensor deployment for efficient ASV designs

Sachin S. Sapatnekar, Jiang Hu, Chaofan Li, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Reliability Analysis of a Delay-Locked Loop Under HCI and BTI Degradation

Sachin S. Sapatnekar, Tonmoy Dhar, 2019, 2019 IEEE International Reliability Physics Symposium (IRPS).

Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints

Sachin S. Sapatnekar, Prashant Saxena, Rupesh S. Shelar, 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Fast and Accurate Statistical Criticality Computation Under Process Variations

Kia Bazargan, Sachin S. Sapatnekar, Haifeng Qian, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Framework for Scalable Postsilicon Statistical Delay Prediction Under Process Variations

Sachin S. Sapatnekar, Qunzeng Liu, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Designing optimized pipelined global interconnects: algorithms and methodology impact

Sachin S. Sapatnekar, Vidyasagar Nookala, S. Sapatnekar, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010

Sachin S. Sapatnekar, S. Sapatnekar, 2010, DAC.

A Customized Graph Neural Network Model for Guiding Analog IC Placement

Sachin S. Sapatnekar, Ramesh Harjani, Yaguang Li, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

A hybrid linear equation solver and its application in quadratic placement

Sachin S. Sapatnekar, Haifeng Qian, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

ReSCALE: Recalibrating sensor circuits for aging and lifetime estimation under BTI

Sachin S. Sapatnekar, Deepashree Sengupta, 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Hierarchical random-walk algorithms for power grid analysis

Sachin S. Sapatnekar, Haifeng Qian, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Adding a new dimension to physical design

Sachin S. Sapatnekar, 2010, ISPD '10.

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

Sachin S. Sapatnekar, Shrirang K. Karandikar, S. Sapatnekar, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Electrothermal analysis and optimization techniques for nanoscale integrated circuits

Sachin S. Sapatnekar, Yong Zhan, Brent Goplen, 2006, Asia and South Pacific Conference on Design Automation, 2006..

A timing model incorporating the effect of crosstalk on delay andits application to optimal channel routing

Sachin S. Sapatnekar, S. Sapatnekar, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Timing Analysis of Sequential Circuits

Sachin S. Sapatnekar, Naresh Maheshwari, 1999 .

Proceedings - Design Automation Conference

Sachin S. Sapatnekar, Vidyasagar Nookala, S. Sapatnekar, 2004, DAC 2004.

Recursive bipartitioning of BDDs for performance driven synthesis of pass transistor logic circuits

Sachin S. Sapatnekar, Rupesh S. Shelar, S. Sapatnekar, 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

Datapath routing based on a decongestion metric

Sachin S. Sapatnekar, Suresh Raman, Charles J. Alpert, 2000, ISPD '00.

Low-power clock distribution using multiple voltages and reduced swings

Sachin S. Sapatnekar, Jatuchai Pangjun, S. Sapatnekar, 2002, IEEE Trans. Very Large Scale Integr. Syst..

Delay and area optimization for discrete gate sizes under double-sided timing constraints

Weitong Chuang, Ibrahim N. Hajj, Sachin S. Sapatnekar, 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

Reinventing EDA with manycore processors

Kurt Keutzer, Sachin S. Sapatnekar, Eshel Haritan, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Global Routing Using Zero-one Integer Linear Programming

Sung-Mo Kang, Sachin S. Sapatnekar, 1993 .

Efficient minarea retiming of large level-clocked circuits

Sachin S. Sapatnekar, Naresh Maheshwari, 1998, Proceedings Design, Automation and Test in Europe.

Timing optimization of mixed static and domino logic

Min Zhao, Sachin S. Sapatnekar, 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

Energy/Delay Tradeoffs in All-Spin Logic Circuits

Sachin S. Sapatnekar, Zhaoxin Liang, 2016, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.

Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001

Sachin S. Sapatnekar, Manfred Wiesel, S. Sapatnekar, 2001, ISPD.

Technology mapping for domino logic

Min Zhao, Sachin S. Sapatnekar, S. Sapatnekar, 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

Topology optimization of structured power/ground networks

Sachin S. Sapatnekar, Jaskirat Singh, 2004, ISPD '04.

A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints

Keshab K. Parhi, Sachin S. Sapatnekar, Vijay Sundararajan, 2004, TODE.

NBTI-Aware Synthesis of Digital Circuits

Sachin S. Sapatnekar, Chris H. Kim, Sanjay V. Kumar, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Microarchitecture-aware floorplanning using a statistical design of experiments approach

Ying Chen, Sachin S. Sapatnekar, David J. Lilja, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Residential task scheduling under dynamic pricing using the multiple knapsack method

Sachin S. Sapatnekar, H. Sivaramakrishnan, N. Kumaraguruparan, 2012, 2012 IEEE PES Innovative Smart Grid Technologies (ISGT).

Guest editorial

Sachin S. Sapatnekar, Charles J. Alpert, Sachin S. Sapatnekar, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A survey on multi-net global routing for integrated circuits

Sachin S. Sapatnekar, Jiang Hu, S. Sapatnekar, 2001, Integr..

Statistical timing analysis with correlated non-Gaussian parameters using independent component analysis

Sachin S. Sapatnekar, Jaskirat Singh, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits

Sachin S. Sapatnekar, Rupesh S. Shelar, S. Sapatnekar, 2002, IWLS.

What happens when circuits grow old: Aging issues in CMOS design

Sachin S. Sapatnekar, 2013, 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Timing-driven partitioning for two-phase domino and mixed static/domino implementations

Min Zhao, Sachin S. Sapatnekar, S. Sapatnekar, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

An exact solution to the transistor sizing problem for CMOS circuits using convex optimization

Sung-Mo Kang, Sachin S. Sapatnekar, Pravin M. Vaidya, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

2.5 A 40×40 Four-Neighbor Time-Based In-Memory Computing Graph ASIC Chip Featuring Wavefront Expansion and 2D Gradient Control

Sachin S. Sapatnekar, Chris H. Kim, Luke R. Everson, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

Layout optimization using arbitrarily high degree posynomial models

Sachin S. Sapatnekar, Piyush K. Sancheti, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Technology mapping algorithm targeting routing congestion under delay constraints

Sachin S. Sapatnekar, Prashant Saxena, Rupesh S. Shelar, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Efficient PEEC-based inductance extraction using circuit-aware techniques

Sachin S. Sapatnekar, Haitian Hu, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

DAC Highlights

Sachin S. Sapatnekar, Grant Martin, A. Kahng, 2005, IEEE Des. Test Comput..

Defining the instruction set architecture

Sachin S. Sapatnekar, David J. Lilja, D. Lilja, 2004 .

Statistical timing analysis under spatial correlations

Sachin S. Sapatnekar, Hongliang Chang, S. Sapatnekar, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems: Guest Editorial

Sachin S. Sapatnekar, Martin D F Wong, Martin D. F. Wong, 2004 .

Efficient In-Memory Processing Using Spintronics

Sachin S. Sapatnekar, Ulya R. Karpuzcu, S. Karen Khatamifard, 2018, IEEE Computer Architecture Letters.

Proceedings of the 47th Design Automation Conference

Sachin S. Sapatnekar, 2010, DAC 2010.

Optimal design of macrocells for low power and high speed

Sachin S. Sapatnekar, Piyush K. Sancheti, P. K. Sancheti, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Optimization and Analysis Techniques for the Deep Submicron Regime

Sachin S. Sapatnekar, Noel Menezes, 2001, VLSI Design.

Probabilistic Congestion Prediction with Partial Blockages

Sachin S. Sapatnekar, Weiping Shi, Charles J. Alpert, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Handbook of Algorithms for Physical Design Automation

Sachin S. Sapatnekar, Dinesh P. Mehta, Charles J. Alpert, 2008 .

Width Quantization Aware FinFET Circuit Design

Jie Gu, Sachin S. Sapatnekar, John Keane, 2006, IEEE Custom Integrated Circuits Conference 2006.

Efficient crosstalk estimation

Keshab K. Parhi, Sachin S. Sapatnekar, Martin Kuhlmann, 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

Temperature-Aware Placement for SOCs

Sung-Mo Kang, Sachin S. Sapatnekar, Haifeng Qian, 2006, Proceedings of the IEEE.

Hierarchical analysis of power distribution networks

Rajendran Panda, David Blaauw, Min Zhao, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A predictive distributed congestion metric with application to technology mapping

Sachin S. Sapatnekar, Prashant Saxena, Rupesh S. Shelar, 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Thermal and Power Delivery Challenges in 3D ICs

Sachin S. Sapatnekar, Pulkit Jain, Chris H. Kim, 2010 .

Random walks in a supply network

Sani R. Nassif, Sachin S. Sapatnekar, Haifeng Qian, 2003, DAC '03.

Minflotransit: min-cost flow based transistor sizing tool

Keshab K. Parhi, Sachin S. Sapatnekar, Vijay Sundararajan, 2000, Proceedings 37th Design Automation Conference.

An Assay of Biochips

Sachin S. Sapatnekar, 2007 .

DAG based library-free technology mapping

Sachin S. Sapatnekar, Felipe S. Marques, Leomar S. da Rosa, 2007, GLSVLSI '07.

Fast Mapping-Based High-Level Synthesis of Pipelined Circuits

Sachin S. Sapatnekar, Jiang Hu, Chaofan Li, 2019, 20th International Symposium on Quality Electronic Design (ISQED).

Clock Skew Optimization

Sachin S. Sapatnekar, Naresh Maheshwari, S. Sapatnekar, 1999 .

An improved algorithm for minimum-area retiming

Sachin S. Sapatnekar, Naresh Maheshwari, 1997, DAC.

INVITED: ALIGN – Open-Source Analog Layout Automation from the Ground Up

Sachin S. Sapatnekar, Jiang Hu, Ramesh Harjani, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

GLARE: Global and local wiring aware routability evaluation

Sachin S. Sapatnekar, Natarajan Viswanathan, Charles J. Alpert, 2012, DAC Design Automation Conference 2012.

A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations

Sachin S. Sapatnekar, Sravan K. Marella, Sanjay V. Kumar, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A Fast and Retargetable Framework for Logic-IP-Internal Electromigration Assessment Comprehending Advanced Waveform Effects

Sachin S. Sapatnekar, Jordi Cortadella, Palkesh Jain, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On the chicken-and-egg problem of determining the effect of crosstalk on delay in integrated circuits

Sachin S. Sapatnekar, 1999, IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412).

High performance CMOS macromodule layout synthesis

Sung-Mo Kang, Sachin S. Sapatnekar, Jaewon Kim, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Energy-Efficient Time-Division Multiplexed Hybrid-Switched NoC for Heterogeneous Multicore Systems

Antonia Zhai, Pingqiang Zhou, Sachin S. Sapatnekar, 2014, 2014 IEEE 28th International Parallel and Distributed Processing Symposium.

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

Sachin S. Sapatnekar, Shrirang K. Karandikar, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Fast on-chip inductance simulation using a precorrected-FFT method

Rajendran Panda, David Blaauw, Min Zhao, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Hierarchical analysis of power distribution networks

Rajendran Panda, Tim Edwards, David Blaauw, 2000, DAC.

A retargetable and accurate methodology for logic-IP-internal electromigration assessment

Sachin S. Sapatnekar, Jordi Cortadella, Palkesh Jain, 2015, The 20th Asia and South Pacific Design Automation Conference.

Adaptive clock with useful jitter

Luciano Lavagno, Sachin S. Sapatnekar, Jordi Cortadella, 2015 .

Clock distribution using multiple voltages

Sachin S. Sapatnekar, Jatuchai Pangjun, S. Sapatnekar, 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

Logical effort based technology mapping

Sachin S. Sapatnekar, Shrirang K. Karandikar, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Book Review: An Assay of Biochips [review of two books: Design Automation Methods and Tools for Microfluidics-Based Biochips (Chakrabarty, K. and Zeng, J., eds.) and BioMEMS (Urban, G.A., ed.)

Sachin S. Sapatnekar, 2007, IEEE Design & Test of Computers.

A systematic approach for analyzing and optimizing cell-internal signal electromigration

Sachin S. Sapatnekar, Gracieli Posser, Ricardo Reis, 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Using Imprecise Computing for Improved Non-Preemptive Real-Time Scheduling

Lin Huang, Sachin S. Sapatnekar, Jiang Hu, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

Stress-Induced Performance Shifts in Flexible System-in-Foils Using Ultra-Thin Chips

Sachin S. Sapatnekar, Tengtao Li, S. Sapatnekar, 2020, 2020 21st International Symposium on Quality Electronic Design (ISQED).

Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs

Sachin S. Sapatnekar, Tengtao Li, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Early-stage power grid analysis for uncertain working modes

Sani R. Nassif, Sachin S. Sapatnekar, Haifeng Qian, 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Statistical Design of Integrated Circuits

Sachin S. Sapatnekar, S. Sapatnekar, 2011, Low-Power Variation-Tolerant Design in Nanometer Silicon.

A methodology for the simultaneous design of supply and signal networks

Sani R. Nassif, Sachin S. Sapatnekar, Jiang Hu, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Learning from Experience: Applying ML to Analog Circuit Design

Sachin S. Sapatnekar, Kishor Kunal, Yaguang Li, 2020, ISPD.

Logical effort based technology mapping

Sachin S. Sapatnekar, S. K. Karandikar, 2004, ICCAD 2004.

Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem

Sachin S. Sapatnekar, Shrirang K. Karandikar, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Physical Design for Three-Dimensional Circuits

Kia Bazargan, Sachin S. Sapatnekar, S. Sapatnekar, 2008, Handbook of Algorithms for Physical Design Automation.

Exploiting Processing in Non-Volatile Memory for Binary Neural Network Accelerators pdf

Sachin S. Sapatnekar, Zhengyang Zhao, Ulya R. Karpuzcu, 2018, ArXiv.

Hybrid structured clock network construction

Sachin S. Sapatnekar, Haihua Su, S. Sapatnekar, 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

Circuit reliability: From Physics to Architectures: Embedded tutorial paper

Pingqiang Zhou, Sachin S. Sapatnekar, Jianxin Fang, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips

Yao-Wen Chang, Chia-Lin Yang, Sachin S. Sapatnekar, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Exact and efficient crosstalk estimation

Sachin S. Sapatnekar, Martin Kuhlmann, S. Sapatnekar, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Joint precision optimization and high level synthesis for approximate computing

Wei Luo, Sachin S. Sapatnekar, Jiang Hu, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Temperature-aware routing in 3D ICs

Sachin S. Sapatnekar, Tianpei Zhang, Yong Zhan, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Efficient calculation of all-pairs input-to-output delays in synchronous sequential circuits

Sachin S. Sapatnekar, 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

Electromigration-Aware Interconnect Design

Sachin S. Sapatnekar, S. Sapatnekar, 2019, ISPD.

Editorial

Sachin S. Sapatnekar, Sachin S. Sapatnekar, 2012, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

The Basics of Retiming

Sachin S. Sapatnekar, Naresh Maheshwari, 1999 .

Capturing Post-Silicon Variations Using a Representative Critical Path

Sachin S. Sapatnekar, Qunzeng Liu, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Spintronic In-Memory Pattern Matching

Sachin S. Sapatnekar, Ulya R. Karpuzcu, Meisam Razaviyayn, 2019, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.

Editorial

Sachin S. Sapatnekar, Sachin S. Sapatnekar, 2011, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Editorial

Sachin S. Sapatnekar, Sachin S. Sapatnekar, 2013, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Interconnect design using convex optimization

Sachin S. Sapatnekar, P. K. Sancheti, S. Sapatnekar, 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

Implementation of the pipelined processor

Sachin S. Sapatnekar, David J. Lilja, D. Lilja, 2004 .

Hierarchical random-walk algorithms for power grid analysis

Sachin S. Sapatnekar, Haifeng Qian, 2004 .

Designing "Vary" Good Circuitry

Sachin S. Sapatnekar, 2005, IEEE Design & Test of Computers.

Using DCT-based Approximate Communication to Improve MPI Performance in Parallel Clusters

Sachin S. Sapatnekar, David J. Lilja, Qianqian Fan, 2019, 2019 IEEE 38th International Performance Computing and Communications Conference (IPCCC).

Transistor Sizing Algorithms: Existing Approaches

Sung-Mo Kang, Sachin S. Sapatnekar, 1993 .

Fast estimation of area-delay trade-offs in circuit sizing

Sachin S. Sapatnekar, Shrirang K. Karandikar, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Metrics Used in Physical Design

Sachin S. Sapatnekar, Frank Liu, S. Sapatnekar, 2008, Handbook of Algorithms for Physical Design Automation.

A quantifiable approach to approximate computing: special session

Sachin S. Sapatnekar, Jiang Hu, Wenbin Xu, 2017, CASES.

Three Dimensional Integrated Circuit Design

Jason Cong, Sachin S. Sapatnekar, Yuan Xie, 2010 .

GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation

Sachin S. Sapatnekar, Saket Gupta, 2012, 17th Asia and South Pacific Design Automation Conference.

A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations

Sachin S. Sapatnekar, Sravan K. Marella, S. Sapatnekar, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

High-performance power grids for nanometer technologies

Sachin S. Sapatnekar, 2004, 17th International Conference on VLSI Design. Proceedings..

Fast disjoint transistor networks from BDDs

Sachin S. Sapatnekar, Felipe S. Marques, Leomar S. da Rosa, 2006, SBCCI '06.

SABER: Selection of approximate bits for the design of error tolerant circuits

Sachin S. Sapatnekar, Jiang Hu, Deepashree Sengupta, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Designing Digital Computer Systems with Verilog: Preface

Sachin S. Sapatnekar, David J. Lilja, D. Lilja, 2004 .

FPGA Synthesis and CAD for Reconfigurable Systems

Luca Benini, Stephen A. Edwards, Yunheung Paek, 2009 .

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited

Kaushik Roy, Anand Raghunathan, Sachin S. Sapatnekar, 2017, DAC.

Using Imprecise Computing for Improved Non-Preemptive Real-Time Scheduling

Sachin S. Sapatnekar, Jiang Hu, Youmeng Li, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

Steiner tree optimization for buffers. Blockages and bays

Sachin S. Sapatnekar, Jiang Hu, José Luis Neves, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Power estimation considering statistical IC parametric variations

Sachin S. Sapatnekar, S. Pilli, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

A Shortest Path Finding Time-Based Accelerator Core With Built-in Gravity Control and Buffer Zone for Smooth 3-D Navigation

Sachin S. Sapatnekar, Chris H. Kim, Luke Everson, 2020, IEEE Solid-State Circuits Letters.

Designing Digital Computer Systems with Verilog: The VASM assembler

Sachin S. Sapatnekar, David J. Lilja, D. Lilja, 2004 .

Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network

Pingqiang Zhou, Sachin S. Sapatnekar, Chris H. Kim, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures

Jason Cong, Sachin S. Sapatnekar, Yuan Xie, 2009 .

Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift

Jie Gu, Sachin S. Sapatnekar, Chris H. Kim, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Optimized Standard Cells for All-Spin Logic

Sachin S. Sapatnekar, Meghna G. Mankalale, 2016, ACM J. Emerg. Technol. Comput. Syst..

Accurate estimation of global buffer delay within a floorplan

Sachin S. Sapatnekar, Jiang Hu, Charles J. Alpert, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Adapting to the times [review of Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.; 2008)]

Sachin S. Sapatnekar, 2008, IEEE Design & Test of Computers.

Wire sizing as a convex optimization problem: exploring the area-delay tradeoff

Sachin S. Sapatnekar, S. Sapatnekar, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

The impact of hot carriers on timing in large circuits

Sachin S. Sapatnekar, Jianxin Fang, 2012, 17th Asia and South Pacific Design Automation Conference.

Impact of Self-heating on Performance and Reliability in FinFET and GAAFET Designs

Sachin S. Sapatnekar, Vidya A. Chhabria, S. Sapatnekar, 2019, 20th International Symposium on Quality Electronic Design (ISQED).

A chip-level electrostatic discharge simulation strategy

Sachin S. Sapatnekar, Haifeng Qian, S. R. Nassif, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits

Sachin S. Sapatnekar, Rahul B. Deokar, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Accurate estimation of global buffer delay within a floorplan

Sachin S. Sapatnekar, Jiang Hu, Charles J. Alpert, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Computer-aided design of 3d integrated circuits

Sachin S. Sapatnekar, 2007, GLSVLSI '07.

Automated module assignment in stacked-Vdd designs for high-efficiency power delivery

Sachin S. Sapatnekar, Yong Zhan, S. Sapatnekar, 2008, JETC.

Clock tree synthesis for multi-chip modules

Sachin S. Sapatnekar, Daksh Lehther, 1996, ICCAD 1996.

Capturing the effect of crosstalk on delay

Sachin S. Sapatnekar, S. Sapatnekar, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Comparing simulation techniques for microarchitecture-aware floorplanning

Ying Chen, Sachin S. Sapatnekar, David J. Lilja, 2006, 2006 IEEE International Symposium on Performance Analysis of Systems and Software.

An Energy Efficient Non-Volatile Flip-Flop based on CoMET Technology

Robert Perricone, Michael Niemier, Sachin S. Sapatnekar, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

BDD decomposition for delay oriented pass transistor logic synthesis

Sachin S. Sapatnekar, Rupesh S. Shelar, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Framework for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers

Sachin S. Sapatnekar, Prithviraj Banerjee, Shankar Ramaswamy, 1994 .

Convexity-based algorithms for design centering

Sung-Mo Kang, Sachin S. Sapatnekar, Pravin M. Vaidya, 1993, ICCAD '93.

High-Efficiency Green Function-Based Thermal Simulation Algorithms

Sachin S. Sapatnekar, Yong Zhan, S. Sapatnekar, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Prediction of leakage power under process uncertainties

Sachin S. Sapatnekar, Hongliang Chang, 2007, TODE.

A fast algorithm for power grid design

Sachin S. Sapatnekar, Jaskirat Singh, 2005, ISPD '05.

PIMBALL: Binary Neural Networks in Spintronic Memory

Sachin S. Sapatnekar, Zhengyang Zhao, Ulya R. Karpuzcu, 2018, ACM Trans. Archit. Code Optim..

Overcoming Variations in Nanometer-Scale Technologies

Sachin S. Sapatnekar, S. Sapatnekar, 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Designing Digital Computer Systems with Verilog: VeSPA Instruction Set

Sachin S. Sapatnekar, David J. Lilja, D. Lilja, 2004 .

Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications

Pingqiang Zhou, Sachin S. Sapatnekar, Chris H. Kim, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Optimized 3D Network-on-Chip Design Using Simulated Allocation

Pingqiang Zhou, Sachin S. Sapatnekar, Ping-Hung Yuh, 2012, TODE.

Compact Current Source Models for Timing Analysis Under Temperature and Body Bias Variations

Sachin S. Sapatnekar, Saket Gupta, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization

Sachin S. Sapatnekar, John P. Fishburn, Harsha Sathyamurthy, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

High efficiency analysis and optimization algorithms in electronic design automation

Sachin S. Sapatnekar, Yong Zhan, 2007 .

Guest Editors' Introduction: New Dimensions in 3D Integration

Kevin J. Nowka, Sachin S. Sapatnekar, 2005, IEEE Des. Test Comput..

An EDA compendium

Sachin S. Sapatnekar, 2005, IEEE Design & Test of Computers.

Incremental solution of power grids using random walks

Sachin S. Sapatnekar, Baktash Boghrati, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Spin-Based Computing: Device Concepts, Current Status, and a Case Study on a High-Performance Microprocessor

Sachin S. Sapatnekar, Chris H. Kim, Jianping Wang, 2015, Proceedings of the IEEE.

CoMET: Composite-Input Magnetoelectric- Based Logic Technology

Sachin S. Sapatnekar, Chris H. Kim, Zhengyang Zhao, 2016, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.

Thermal Via Insertion and Thermally Aware Routing in 3D ICs

Sachin S. Sapatnekar, 2010 .

Proceedings of the International Symposium on Physical Design: Foreword

Massoud Pedram, Sachin S. Sapatnekar, S. Sapatnekar, 2001 .

Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic

Min Zhao, Sachin S. Sapatnekar, S. Sapatnekar, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

A predictive distributed congestion metric with application to technology mapping

Sachin S. Sapatnekar, Prashant Saxena, Rupesh S. Shelar, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Best Paper in the Front-End Design Category Session 10.5: "The Synthesis of Cyclic Combinational Circuits"

Sani R. Nassif, Sachin S. Sapatnekar, Marc D. Riedel, 2003 .

Probabilistic Wire Resistance Degradation Due to Electromigration in Power Grids

Sachin S. Sapatnekar, Vivek Mishra, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An integrated algorithm for combined placement and libraryless technology mapping

Sachin S. Sapatnekar, Yanbin Jiang, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

A new structural pattern matching algorithm for technology mapping

Min Zhao, Sachin S. Sapatnekar, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

True In-memory Computing with the CRAM: From Technology to Applications

Sachin S. Sapatnekar, Zhengyang Zhao, Ulya R. Karpuzcu, 2019, ACM Great Lakes Symposium on VLSI.

Standby power optimization via transistor sizing and dual threshold voltage assignment

Sachin S. Sapatnekar, Mahesh Ketkar, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Scalable Methods for Analyzing the Circuit Failure Probability Due to Gate Oxide Breakdown

Sachin S. Sapatnekar, Jianxin Fang, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal

Sachin S. Sapatnekar, Hongliang Chang, 2003, ICCAD 2003.

A high efficiency full-chip thermal simulation algorithm

Sachin S. Sapatnekar, Yong Zhan, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Optimization of FinFET-based circuits using a dual gate pitch technique

Sachin S. Sapatnekar, Saibal Mukhopadhyay, Amit Ranjan Trivedi, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A timing-constrained algorithm for simultaneous global routing of multiple nets

Sachin S. Sapatnekar, Jiang Hu, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

A graph-theoretic approach to clock skew optimization

Sachin S. Sapatnekar, Rahul B. Deokar, S. Sapatnekar, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Early-stage power grid analysis for uncertain working modes

Sani R. Nassif, Sachin S. Sapatnekar, Haifeng Qian, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Standby power optimization via transistor sizing and dual threshold voltage assignment

Sachin S. Sapatnekar, Mahesh Ketkar, 2002, ICCAD 2002.

Technical perspectiveWhere the chips may fall

Sachin S. Sapatnekar, 2009, Commun. ACM.

Stochastic and topologically aware electromigration analysis for clock skew

Sachin S. Sapatnekar, Jordi Cortadella, Palkesh Jain, 2015, 2015 IEEE International Reliability Physics Symposium.

Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing

Sachin S. Sapatnekar, John Keane, Chris H. Kim, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

SeFAct2: Selective Feature Activation for Energy-Efficient CNNs Using Optimized Thresholds

Sachin S. Sapatnekar, Jiang Hu, Farhana Sharmin Snigdha, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

FAR-DS: full-plane AWE routing with driver sizing

Sachin S. Sapatnekar, Jiang Hu, 1999, DAC '99.

Thermally-Aware Design

Sachin S. Sapatnekar, Yong Zhan, Sanjay V. Kumar, 2008 .

An Analytical Approach for Error PMF Characterization in Approximate Circuits

Sachin S. Sapatnekar, Jiang Hu, Deepashree Sengupta, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Introduction to Physical Design

Sachin S. Sapatnekar, Dinesh P. Mehta, Charles J. Alpert, 2008, Handbook of Algorithms for Physical Design Automation.

An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts

Sani R. Nassif, Sachin S. Sapatnekar, Haihua Su, 2002, ISPD '02.

Circuit Performance Shifts Due to Layout-Dependent Stress in Planar and 3D-ICs

Sachin S. Sapatnekar, Sravan K. Marella, S. Sapatnekar, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Placement of 3D ICs with Thermal and Interlayer Via Considerations

Sachin S. Sapatnekar, Brent Goplen, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Building an assembler for VeSPA

Sachin S. Sapatnekar, David J. Lilja, D. Lilja, 2004 .

Marsh:min-area retiming with setup and hold constraints

Keshab K. Parhi, Sachin S. Sapatnekar, Vijay Sundararajan, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Optimizing large multiphase level-clocked circuits

Sachin S. Sapatnekar, Naresh Maheshwari, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Design by optimization

Sachin S. Sapatnekar, S. Sapatnekar, 2009 .

An efficient algorithm for low power pass transistor logic synthesis

Sachin S. Sapatnekar, Rupesh S. Shelar, S. Sapatnekar, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Editorial to special issue DAC 2006

Sachin S. Sapatnekar, Krishnendu Chakrabarty, 2007, JETC.

Electromigration Inside Logic Cells: Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS

Sachin S. Sapatnekar, Gracieli Posser, Ricardo Reis, 2016 .

Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits

Sachin S. Sapatnekar, Chris H. Kim, Sanjay V. Kumar, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Steiner tree optimization for buffers, blockages, and bays

Sachin S. Sapatnekar, Jiang Hu, José Luis Neves, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Module assignment for pin-limited designs under the stacked-Vdd paradigm

Sachin S. Sapatnekar, Tianpei Zhang, Yong Zhan, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

CRAFFT: High Resolution FFT Accelerator In Spintronic Computational RAM

Sachin S. Sapatnekar, Zamshed Iqbal Chowdhury, Masoud Zabihi, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

Logic and memory design using spin-based circuits

Sachin S. Sapatnekar, Zhaoxin Liang, Meghna G. Mankalale, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Adaptive-Length Coding of Image Data for Low-Cost Approximate Storage

Sachin S. Sapatnekar, David J. Lilja, Qianqian Fan, 2020, IEEE Transactions on Computers.

International Symposium on Physical Design (ISPD)

Andrew B. Kahng, Sachin S. Sapatnekar, Jiang Hu, 2002, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A practical methodology for early buffer and wire resource allocation

Sachin S. Sapatnekar, Jiang Hu, Charles J. Alpert, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

A general approach for identifying hierarchical symmetry constraints for analog circuit layout

Sachin S. Sapatnekar, Tonmoy Dhar, Kishor Kunal, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

A fresh look at retiming via clock skew optimization

Sachin S. Sapatnekar, Rahul B. Deokar, 1995, DAC '95.

An efficient algorithm for calculating the worst-case delay due to crosstalk

Sachin S. Sapatnekar, Venkatesan Rajappan, 2003, Proceedings 21st International Conference on Computer Design.

Efficient inductance extraction using circuit-aware techniques

Sachin S. Sapatnekar, Haitian Hu, 2002, IEEE Trans. Very Large Scale Integr. Syst..

Incorporating the role of stress on electromigration in power grids with via arrays

Sachin S. Sapatnekar, Vivek Mishra, Palkesh Jain, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Reducing the signal Electromigration effects on different logic gates by cell layout optimization

Sachin S. Sapatnekar, Gracieli Posser, Ricardo Reis, 2015, 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS).

A fixed-die floorplanning algorithm using an analytical approach

Yan Feng, Sachin S. Sapatnekar, Yong Zhan, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Impact of NBTI on SRAM read stability and design for reliability

Sachin S. Sapatnekar, Chris H. Kim, Sanjay V. Kumar, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks pdf

Sachin S. Sapatnekar, Palkesh Jain, Nikhil Patil, 2020, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

Technology mapping for high-performance static CMOS and pass transistor logic designs

Sachin S. Sapatnekar, Cyrus Bamji, Yanbin Jiang, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Buffering global interconnects in structured ASIC design

Sachin S. Sapatnekar, Tianpei Zhang, S. Sapatnekar, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing

Sachin S. Sapatnekar, Tianpei Zhang, S. Sapatnekar, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Buffering global interconnects in structured ASIC design

Sachin S. Sapatnekar, Tianpei Zhang, 2008, Integr..

IEEE Journal on Emerging and Selected Topics in Circuits and Systems information for authors

Jason Cong, Ronald Tetzlaff, Gert Cauwenberghs, 2018, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach

Sachin S. Sapatnekar, Brent Goplen, 2003, ICCAD.

Tradeoffs between gate oxide leakage and delay for dual T/sub ox/ circuits

Dennis Sylvester, Sachin S. Sapatnekar, Anup Kumar Sultania, 2004, Proceedings. 41st Design Automation Conference, 2004..

A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic

Sachin S. Sapatnekar, Cyrus Bamji, Yanbin Jiang, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

Dummy fill optimization for enhanced manufacturability

Sachin S. Sapatnekar, Yaoguang Wei, 2010, ISPD '10.

Design Automation for Timing-Driven Layout Synthesis

Sung-Mo Kang, Sachin S. Sapatnekar, 1992 .

Timing Analysis and Optimization of Sequential Circuits

Sachin S. Sapatnekar, Naresh Maheshwari, 1998 .

A Convex Programming Approach to Transistor Sizing

Sung-Mo Kang, Sachin S. Sapatnekar, 1993 .

GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits

Sachin S. Sapatnekar, Tonmoy Dhar, Kishor Kunal, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Placement optimization of power supply pads based on locality

Pingqiang Zhou, Sachin S. Sapatnekar, Vivek Mishra, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Thermal via placement in 3D ICs

Sachin S. Sapatnekar, Brent Goplen, S. Sapatnekar, 2005, ISPD '05.

iDEAS: a delay estimator and transistor sizing tool for CMOS circuits

Sachin S. Sapatnekar, V. B. Rao, S. Sapatnekar, 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation Platform

Sachin S. Sapatnekar, Zhengyang Zhao, Ulya R. Karpuzcu, 2019, 20th International Symposium on Quality Electronic Design (ISQED).

The Certainty of Uncertainty: Randomness in Nanometer Design

Sachin S. Sapatnekar, Haifeng Qian, Hongliang Chang, 2004, PATMOS.

High-speed interconnect technology: on-chip and off-chip

Sachin S. Sapatnekar, Ramesh Harjani, Jaijeet S. Roychowdhury, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Editorial

Sachin S. Sapatnekar, Sachin S. Sapatnekar, 2013, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Fast Poisson solvers for thermal analysis

Sachin S. Sapatnekar, Eren Kursun, Haifeng Qian, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Partition-driven standard cell thermal placement

Sachin S. Sapatnekar, Guoqiang Chen, S. Sapatnekar, 2003, ISPD '03.

Power Grid Analysis

Sachin S. Sapatnekar, S. Sapatnekar, 2016, Encyclopedia of Algorithms.

Analysis and optimization of structured power/ground networks

Sachin S. Sapatnekar, Kaushik Gala, Haihua Su, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations

Sachin S. Sapatnekar, Qunzeng Liu, 2007, 2007 44th ACM/IEEE Design Automation Conference.

CAD for 3D circuits: Solutions and challenges

Sachin S. Sapatnekar, 2007 .

Timing-driven partitioning and timing optimization of mixedstatic-domino implementations

Min Zhao, Sachin S. Sapatnekar, S. Sapatnekar, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Timing-driven CMOS Layout Synthesis

Sung-Mo Kang, Sachin S. Sapatnekar, 1993 .

FEMTO: Fast error analysis in Multipliers through Topological Traversal

Sachin S. Sapatnekar, Deepashree Sengupta, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Interleaving buffer insertion and transistor sizing into a single optimization

Sachin S. Sapatnekar, Juho Kim, Cyrus Bamji, 1998, IEEE Trans. Very Large Scale Integr. Syst..

Wiresizing with buffer placement and sizing for power-delay tradeoffs

Sachin S. Sapatnekar, Jatan C. Shah, S. Sapatnekar, 1996, Proceedings of 9th International Conference on VLSI Design.

Non-Hanan routing

Sachin S. Sapatnekar, Jiang Hu, Huibo Hou, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Physical design techniques for optimizing RTA-induced variations

Sachin S. Sapatnekar, Jiang Hu, Frank Liu, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

A Convex Programming Approach for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers

Sachin S. Sapatnekar, Prithviraj Banerjee, Shankar Ramaswamy, 1994, 1994 Internatonal Conference on Parallel Processing Vol. 2.

A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area

Weitong Chuang, Ibrahim N. Hajj, Sachin S. Sapatnekar, 1993, ICCAD.

Static Timing Analysis

Sachin S. Sapatnekar, Jordi Cortadella, S. Sapatnekar, 2017 .

Synthesizing a representative critical path for post-silicon delay prediction

Sachin S. Sapatnekar, Qunzeng Liu, 2009, ISPD '09.

Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors

Pingqiang Zhou, Sachin S. Sapatnekar, Karthikk Sridharan, 2009, 2009 Asia and South Pacific Design Automation Conference.

A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation

Zhi-Quan Luo, Sachin S. Sapatnekar, Jaskirat Singh, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Full-chip analysis of leakage power under process variations, including spatial correlations

Sachin S. Sapatnekar, Hongliang Chang, S. Sapatnekar, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Convex delay models for transistor sizing

Sachin S. Sapatnekar, Mahesh Ketkar, Kishore Kasamsetty, 2000, DAC.

Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs

Sachin S. Sapatnekar, Juho Kim, Cyrus Bamji, 1997, ISPD '97.

Variation-Aware Variable Latency Design

Sachin S. Sapatnekar, Saket Gupta, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Computing-in-memory with spintronics

Kaushik Roy, Anand Raghunathan, Sachin S. Sapatnekar, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates]

Sachin S. Sapatnekar, Mahesh Ketkar, Kishore Kasamsetty, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform

Sachin S. Sapatnekar, Ulya R. Karpuzcu, Masoud Zabihi, 2020, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.

Application-specific 3D Network-on-Chip design using simulated allocation

Pingqiang Zhou, Sachin S. Sapatnekar, Ping-Hung Yuh, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Temperature-Aware Floorplanning of Microarchitecture Blocks with IPC-Power Dependence Modeling and Transient Analysis

Sachin S. Sapatnekar, David J. Lilja, Vidyasagar Nookala, 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

Layout Optimization in VLSI Design

Sachin S. Sapatnekar, Dingzhu Du, Bing Lu, 2001, Network Theory and Applications.

Designing Digital Computer Systems with Verilog

Sachin S. Sapatnekar, David J. Lilja, D. Lilja, 2004 .

Power Grid Optimization in 3D Circuits Using MIM and CMOS Decoupling Capacitors

Sachin S. Sapatnekar, Pingqiang Zhou, Karthikk Sridharan, 2011 .

Placement of thermal vias in 3-D ICs using various thermal objectives

Sachin S. Sapatnekar, Brent Goplen, S. Sapatnekar, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Radu Marculescu, Majid Sarrafzadeh, Vishwani D. Agrawal, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Impact on performance, power, area and wirelength using electromigration-aware cells

Sachin S. Sapatnekar, Gracieli Posser, Ricardo Reis, 2015, 2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS).

IEEE Journal on Emerging and Selected Topics in Circuits and Systems: Guest editorial

Sachin S. Sapatnekar, S. Sapatnekar, 2011 .

Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors

Sachin S. Sapatnekar, Chris H. Kim, Saket Gupta, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity

Pingqiang Zhou, Sachin S. Sapatnekar, Karthikk Sridharan, 2009, IEEE Design & Test of Computers.

AgELESS: Aging estimation and lifetime enhancement in silicon systems

Sachin S. Sapatnekar, 2015 .

The whys and hows of thermal management

Sachin S. Sapatnekar, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

Improving QoS for Global Dual-Criticality Scheduling on Multiprocessors

Sachin S. Sapatnekar, Jiang Hu, I-Hong Hou, 2019, 2019 IEEE 25th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA).

Exact lower bound for the number of switches in series to implement a combinational logic cell

Sachin S. Sapatnekar, Renato P. Ribas, André Inácio Reis, 2005, 2005 International Conference on Computer Design.

Improving STT-MRAM density through multibit error correction

Sachin S. Sapatnekar, Chris H. Kim, Jongyeon Kim, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Power-delay optimizations in gate sizing

Weitong Chuang, Sachin S. Sapatnekar, S. Sapatnekar, 2000, TODE.

Fast comparisons of circuit implementations

Sachin S. Sapatnekar, Shrirang K. Karandikar, 2004 .

A Framework for Exploiting Task and Data Parallelism on Distributed Memory Multicomputers

Sachin S. Sapatnekar, Prithviraj Banerjee, Shankar Ramaswamy, 1997, IEEE Trans. Parallel Distributed Syst..

A scaled random walk solver for fast power grid analysis

Sachin S. Sapatnekar, Baktash Boghrati, 2011, 2011 Design, Automation & Test in Europe.

Ring Oscillator Clocks and Margins

Sachin S. Sapatnekar, Alberto Moreno-Conde, Jordi Cortadella, 2016, 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC).

Estimating Circuit Aging Due to BTI and HCI Using Ring-Oscillator-Based Sensors

Sachin S. Sapatnekar, Deepashree Sengupta, S. Sapatnekar, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Incremental Analysis of Power Grids Using Backward Random Walks

Sachin S. Sapatnekar, Baktash Boghrati, S. Sapatnekar, 2014, TODE.

Statistical timing analysis considering spatial correlations using a single PERT-like traversal

Sachin S. Sapatnekar, Hongliang Chang, S. Sapatnekar, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application Mapping

Sachin S. Sapatnekar, Zhengyang Zhao, Ulya R. Karpuzcu, 2019, IEEE Transactions on Computers.

Gate size optimization for row-based layouts

Sachin S. Sapatnekar, Naresh Maheshwari, 1995, 38th Midwest Symposium on Circuits and Systems. Proceedings.

Current source modeling in the presence of body bias

Sachin S. Sapatnekar, Saket Gupta, S. Sapatnekar, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Computer-Aided Design for 3D Circuits at the University of Minnesota

Sachin S. Sapatnekar, S. Sapatnekar, 2008 .

Fast comparisons of circuit implementations

Sachin S. Sapatnekar, Shrirang K. Karandikar, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Fast analysis and optimization of power/ground networks

Sachin S. Sapatnekar, Kaushik Gala, Haihua Su, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Predicting circuit aging using ring oscillators

Sachin S. Sapatnekar, Deepashree Sengupta, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

Net weighting to reduce repeater counts during placement

Sachin S. Sapatnekar, Prashant Saxena, Brent Goplen, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems

Sachin S. Sapatnekar, Chris H. Kim, Sanjay V. Kumar, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Variability and Statistical Design (IPSJ Transactions on System LSI Design Methodology Vol.1)

Sachin S. Sapatnekar, S. Sapatnekar, 2008 .

Analyzing the electromigration effects on different metal layers and different wire lengths

Sachin S. Sapatnekar, Gracieli Posser, Ricardo Augusto da Luz Reis, 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Placement and routing in 3D integrated circuits

Kia Bazargan, Yan Feng, Sachin S. Sapatnekar, 2005, IEEE Design & Test of Computers.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Sachin S. Sapatnekar, Yong Zhan, Yan Feng, 2006 .

Analysis and optimization of power grids

Sachin S. Sapatnekar, Haihua Su, 2003, IEEE Design & Test of Computers.

Empowering the designer

Sachin S. Sapatnekar, S. Sapatnekar, 2005, IEEE Design & Test of Computers.

Transistor and pin reordering for gate oxide leakage reduction in dual T/sub ox/ circuits

Dennis Sylvester, Sachin S. Sapatnekar, Anup Kumar Sultania, 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

NoC frequency scaling with flexible-pipeline routers

Antonia Zhai, Pingqiang Zhou, Sachin S. Sapatnekar, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

Routing Congestion in VLSI Circuits - Estimation and Optimization

Sachin S. Sapatnekar, Prashant Saxena, Rupesh S. Shelar, 2007, Series on Integrated Circuits and Systems.

Miscellaneous Issues in Retiming

Sachin S. Sapatnekar, Naresh Maheshwari, 1999 .

Power vs. delay in gate sizing: conflicting objectives?

Weitong Chuang, Sachin S. Sapatnekar, S. Sapatnekar, 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

A new approach to the use of satisfiability in false path detection

Sachin S. Sapatnekar, Felipe S. Marques, Renato P. Ribas, 2005, GLSVLSI '05.

Optimal decoupling capacitor sizing and placement for standard-cell layout designs

Sani R. Nassif, Sachin S. Sapatnekar, Haihua Su, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Techniques for scalable and effective routability evaluation

Sachin S. Sapatnekar, Natarajan Viswanathan, Charles J. Alpert, 2014, TODE.

Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations

Sachin S. Sapatnekar, Chris H. Kim, Ayan Paul, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

Congestion-driven codesign of power and signal networks

Sani R. Nassif, Sachin S. Sapatnekar, Jiang Hu, 2002, DAC '02.

Error Analysis and Optimization in Approximate Arithmetic Circuits

Sachin S. Sapatnekar, Jiang Hu, Deepashree Sengupta, 2019, Approximate Circuits.

Addressing thermal and power delivery bottlenecks in 3D circuits

Sachin S. Sapatnekar, S. Sapatnekar, 2009, 2009 Asia and South Pacific Design Automation Conference.

Employing circadian rhythms to enhance power and reliability

Sachin S. Sapatnekar, Saket Gupta, 2013, TODE.

Clustering based pruning for statistical criticality computation under process variations

Kia Bazargan, Sachin S. Sapatnekar, Haifeng Qian, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

SeFAct: selective feature activation and early classification for CNNs

Sachin S. Sapatnekar, Jiang Hu, Ibrahim Ahmed, 2019, ASP-DAC.

ALIGN: A System for Automating Analog Layout pdf

Sachin S. Sapatnekar, Tonmoy Dhar, Kishor Kunal, 2020, IEEE Design & Test.

Retiming control logic

Sachin S. Sapatnekar, Naresh Maheshwari, 1999, Integr..

Performance Characterization and Majority Gate Design for MESO-Based Circuits

Sachin S. Sapatnekar, Zhengyang Zhao, Jiaxi Hu, 2018, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.

Clustering based pruning for statistical criticality computation under process variations

Kia Bazargan, Sachin S. Sapatnekar, Haifeng Qian, 2007, ICCAD 2007.

Performance Driven Global Routing Through Gradual Refinement

Sachin S. Sapatnekar, Jiang Hu, 2002, VLSI Design.

Robust gate sizing by geometric programming

Zhi-Quan Luo, Sachin S. Sapatnekar, Jaskirat Singh, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Circuit delay variability due to wire resistance evolution under AC electromigration

Sachin S. Sapatnekar, Vivek Mishra, S. Sapatnekar, 2015, 2015 IEEE International Reliability Physics Symposium.

A simple yet efficient accuracy configurable adder design

Sachin S. Sapatnekar, Jiang Hu, Wenbin Xu, 2017, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Session details: Advances in boundary element methods for parasitic extraction

Sachin S. Sapatnekar, Yehea Ismail, J. Eric Bracken, 2005, DAC 2005.

Computational RAM to Accelerate String Matching at Scale pdf

Sachin S. Sapatnekar, Zhengyang Zhao, Ulya R. Karpuzcu, 2018, ArXiv.

Performance driven global routing through gradual refinement

Sachin S. Sapatnekar, Jiang Hu, 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

RC Interconnect Optimization under the Elmore Delay Model

Sachin S. Sapatnekar, S. Sapatnekar, 1994, 31st Design Automation Conference.

Incorporating Hot-Carrier Injection Effects Into Timing Analysis for Large Circuits

Sachin S. Sapatnekar, Jianxin Fang, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Optimization of integrated spiral inductors using sequential quadratic programming

Sachin S. Sapatnekar, Yong Zhan, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

BTI-aware design using variable latency units

Sachin S. Sapatnekar, Saket Gupta, 2012, 17th Asia and South Pacific Design Automation Conference.

Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up

Sachin S. Sapatnekar, Yong Zhan, S. Sapatnekar, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Technology mapping algorithms for domino logic

Min Zhao, Sachin S. Sapatnekar, S. Sapatnekar, 2002, TODE.

Body Bias Voltage Computations for Process and Temperature Compensation

Sachin S. Sapatnekar, Chris H. Kim, Sanjay V. Kumar, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Invited: Optimizing device reliability effects at the intersection of physics, circuits, and architecture

Sachin S. Sapatnekar, Vivek Mishra, Deepashree Sengupta, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

SkyLogic—A Proposal for a Skyrmion-Based Logic Device

Sachin S. Sapatnekar, Zhengyang Zhao, Jianping Wang, 2018, IEEE Transactions on Electron Devices.

A practical methodology for early buffer and wire resource allocation

Sachin S. Sapatnekar, Jiang Hu, Charles J. Alpert, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Advanced spintronic memory and logic for non-volatile processors

Robert Perricone, Sachin S. Sapatnekar, Michael T. Niemier, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

RTL Synthesis: From Logic Synthesis to Automatic

Sachin S. Sapatnekar, Jordi Cortadella, Michael Kishinevsky, 2015 .

Temperature as a first-class citizen in chip design

Sachin S. Sapatnekar, 2009, 2009 15th International Workshop on Thermal Investigations of ICs and Systems.

Routing tree topology construction to meet interconnect timing constraints

Sachin S. Sapatnekar, Huibo Hou, S. Sapatnekar, 1998, ISPD '98.

Reactive clocks with variability-tracking jitter

Luciano Lavagno, Sachin S. Sapatnekar, Alberto Moreno-Conde, 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

Module assignment for pin-limited designs under the stacked-Vdd paradigm

Sachin S. Sapatnekar, Tianpei Zhang, Yong Zhan, 2007, ICCAD 2007.

In Memoriam: Margarida F. Jacome

Gustavo de Veciana, Enrico Macii, Sachin S. Sapatnekar, 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Clock tree synthesis for multi-chip modules

Sachin S. Sapatnekar, Daksh Lehther, 1996, Proceedings of International Conference on Computer Aided Design.

Thermal signature: A simple yet accurate thermal index for floorplan optimization

Sachin S. Sapatnekar, Youngsoo Shin, Jaeha Kung, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Power grid analysis using random walks

Sani R. Nassif, Sachin S. Sapatnekar, Haifeng Qian, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Strain-Aware Performance Evaluation and Correction for OTFT-Based Flexible Displays

Sachin S. Sapatnekar, Tengtao Li, S. Sapatnekar, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Accurate estimation of global buffer delay within a floorplan

Sachin S. Sapatnekar, Jiang Hu, Charles J. Alpert, 2004, ICCAD 2004.

Fast and exact transistor sizing based on iterative relaxation

Keshab K. Parhi, Sachin S. Sapatnekar, Vijay Sundararajan, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

STEM: A Scheme for Two-Phase Evaluation of Majority Logic

Sachin S. Sapatnekar, Zhaoxin Liang, Meghna G. Mankalale, 2017, IEEE Transactions on Nanotechnology.

A simple yet efficient accuracy configurable adder design

Sachin S. Sapatnekar, Jiang Hu, Wenbin Xu, 2017, ISLPED.

MOUSE: Inference In Non-volatile Memory for Energy Harvesting Applications

Sachin S. Sapatnekar, Ulya R. Karpuzcu, S. Karen Khatamifard, 2020, 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Timing and area optimization for standard-cell VLSI circuit design

Weitong Chuang, Ibrahim N. Hajj, Sachin S. Sapatnekar, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A Linear-Time Algorithm for Steady-State Analysis of Electromigration in General Interconnects pdf

Sachin S. Sapatnekar, Vidya A. Chhabria, Mohammad Abdullah Al Shohel, 2021, ArXiv.

Machine Learning Techniques in Analog Layout Automation

Sachin S. Sapatnekar, Ramesh Harjani, Tonmoy Dhar, 2021, ISPD.

VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis

Andrew B. Kahng, Sachin S. Sapatnekar, Hadi Esmaeilzadeh, 2021, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing

Sachin S. Sapatnekar, Ramesh Harjani, Yishuang Lin, 2021, 2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD).

From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning

Sachin S. Sapatnekar, Ramesh Harjani, Meghna Madhusudan, 2021, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Analytical Modeling of Transient Electromigration Stress based on Boundary Reflections

Sachin S. Sapatnekar, Nestoras E. Evmorfopoulos, Vidya A. Chhabria, 2021, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Exploring the Feasibility of Using 3-D XPoint as an In-Memory Computing Accelerator

Sachin S. Sapatnekar, Ulya R. Karpuzcu, Masoud Zabihi, 2021, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.

GNNIE: GNN Inference Engine with Load-balancing and Graph-Specific Caching pdf

Sachin S. Sapatnekar, Kishor Kunal, Susmita Dey Manasi, 2021, ArXiv.

Common-Centroid Layouts for Analog Circuits: Advantages and Limitations

Sachin S. Sapatnekar, Ramesh Harjani, Meghna Madhusudan, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Spiking Neural Networks in Spintronic Computational RAM

Keshab K. Parhi, Sachin S. Sapatnekar, Ulya R. Karpuzcu, 2021, ACM Trans. Archit. Code Optim..

DeepOpt: Optimized Scheduling of CNN Workloads for ASIC-based Systolic Deep Learning Accelerators

Sachin S. Sapatnekar, Susmita Dey Manasi, S. Sapatnekar, 2021, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

Analog Layout Generation using Optimized Primitives

Sachin S. Sapatnekar, Meghna Madhusudan, Jiang Hu, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology

Sachin S. Sapatnekar, Kishor Kunal, Masoud Zabihi, 2021, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient Control

Sachin S. Sapatnekar, Chris H. Kim, Luke R. Everson, 2021, IEEE Journal of Solid-State Circuits.

Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits

Sachin S. Sapatnekar, Ramesh Harjani, Meghna Madhusudan, 2021, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Aging of Current DACs and its Impact in Equalizer Circuits

Sachin S. Sapatnekar, Ramesh Harjani, Tonmoy Dhar, 2021, 2021 IEEE International Reliability Physics Symposium (IRPS).

CAMeleon: Reconfigurable B(T)CAM in Computational RAM

Sachin S. Sapatnekar, Ulya R. Karpuzcu, Masoud Zabihi, 2021, ACM Great Lakes Symposium on VLSI.

OpeNPDN: A Neural-Network-Based Framework for Power Delivery Network Synthesis pdf

Sachin S. Sapatnekar, Vidya A. Chhabria, S. Sapatnekar, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks pdf

Sachin S. Sapatnekar, Palkesh Jain, Vidya A. Chhabria, 2021, ACM Trans. Design Autom. Electr. Syst..

Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models

Sachin S. Sapatnekar, Ramesh Harjani, Tonmoy Dhar, 2021, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

Towards Homomorphic Inference Beyond the Edge pdf

Sachin S. Sapatnekar, Ulya R. Karpuzcu, Masoud Zabihi, 2021, ArXiv.

Circuit reliability: from physics to architectures

Pingqiang Zhou, Sachin S. Sapatnekar, Vivek Mishra, 2012, ICCAD '12.

NonHanan Routing

Sachin S. Sapatnekar, Jiang Hu, Huibo Hou, 1998 .

Wiresizing with Bu er Placement and Sizing for Power-Delay Tradeo s

Sachin S. Sapatnekar, Jatan C. Shah, S. Sapatnekar, 1996 .

An algorithm for simulating power/ground networks using Pade approximants and its symbolic implementation

Sachin S. Sapatnekar, M. M. Hassoun, J. C. Shah, 1998 .

E cient Calculation of All-Pairs Input-to-Output Delays in Synchronous Sequential Circuits

Sachin S. Sapatnekar, 1999 .

Stochastic and hybrid linear equation solvers and their applications in vlsi design automation

Sachin S. Sapatnekar, S. Sapatnekar, Haifeng Qian, 2006 .

A fast magnetoelectric device based on current-driven domain wall propagation

Sachin S. Sapatnekar, Mahdi Jamali, Zhaoxin Liang, 2016, 2016 74th Annual Device Research Conference (DRC).

INVITED : A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era

Kaushik Roy, Michael Niemier, Sachin S. Sapatnekar, 2017 .

A Comparative Study Between Spin-Transfer-Torque and Spin-Hall-Effect Switching Mechanisms in PMTJ Using SPICE

Sachin S. Sapatnekar, Chris H. Kim, Zhengyang Zhao, 2017, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.

A Framework for Scalable Post-Silicon Statistical Delay Prediction under Spatial Variations

Sachin S. Sapatnekar, Qunzeng Liu, 2009 .

Realizable reduction of passive networks

Sachin S. Sapatnekar, Yousef Saad, Bernard N. Sheehan, 2005 .

International Symposium on Physical Design (ISPD)

Andrew B. Kahng, Sachin S. Sapatnekar, Jiang Hu, 2002, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Circuit timing and leakage power analysis under process variations

Sachin S. Sapatnekar, Hongliang Chang, S. Sapatnekar, 2006 .

A general model for performance optimization of sequential systems

Sachin S. Sapatnekar, Jordi Cortadella, Michael Kishinevsky, 2007, ICCAD 2007.

A Survey of SSTA Techniques with Focus on Accuracy and Speed

Sachin S. Sapatnekar, Vladimir Zolotov, Daniel K. Beece, 2017 .