Rajesh Inti

发表

A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance

Amr Elshazly, Pavan Kumar Hanumolu, Wenjing Yin, 2011, 2011 IEEE International Solid-State Circuits Conference.

A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance

Amr Elshazly, Pavan Kumar Hanumolu, Wenjing Yin, 2011, IEEE Journal of Solid-State Circuits.

A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS

Thomas Toifl, Christian Menolfi, Matthias Braendli, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

A 4–32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS

Shreyas Sen, James E. Jaussi, Bryan Casper, 2014, IEEE Journal of Solid-State Circuits.

A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking

Amr Elshazly, Pavan Kumar Hanumolu, Wenjing Yin, 2011, IEEE Journal of Solid-State Circuits.

A Digital-Intensive 2-to-9.2 GB/S/Pin Memory Controller I/O with Fast-Response LDO in 10NM CMOS

James E. Jaussi, Bryan Casper, Joe Kennedy, 2018, 2018 IEEE Symposium on VLSI Circuits.

A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery

Amr Elshazly, Pavan Kumar Hanumolu, Wenjing Yin, 2011, IEEE Journal of Solid-State Circuits.

A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration

Amr Elshazly, Pavan Kumar Hanumolu, Wenjing Yin, 2011, IEEE Journal of Solid-State Circuits.

A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, −55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC

Amr Elshazly, Pavan Kumar Hanumolu, Brian Young, 2012, 2012 IEEE International Solid-State Circuits Conference.

A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery

Amr Elshazly, Pavan Kumar Hanumolu, Wenjing Yin, 2011, 2011 IEEE International Solid-State Circuits Conference.

A 16-mW 78-dB SNDR 10-MHz BW CT $\Delta \Sigma$ ADC Using Residue-Cancelling VCO-Based Quantizer

Amr Elshazly, Pavan Kumar Hanumolu, Brian Young, 2012, IEEE Journal of Solid-State Circuits.

A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer

Amr Elshazly, Pavan Kumar Hanumolu, Brian Young, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 1.6mW 1.6ps-rms-jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS

Pavan Kumar Hanumolu, Wenjing Yin, Rajesh Inti, 2010, IEEE Custom Integrated Circuits Conference 2010.

Digital clock and data recovery circuit design: Challenges and tradeoffs

Pavan Kumar Hanumolu, Rajesh Inti, Mrunmay Talegaonkar, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop

Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu, 2014, IEEE Journal of Solid-State Circuits.

Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops

Amr Elshazly, Pavan Kumar Hanumolu, Brian Young, 2013, IEEE Journal of Solid-State Circuits.

Low-noise self-referenced CMOS oscillator

Pavan Kumar Hanumolu, Rajesh Inti, N. Sasidhar, 2009 .

A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control

Amr Elshazly, Pavan Kumar Hanumolu, Sachin Rao, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS

Joseph Kennedy, Shreyas Sen, Tawfiq Musah, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

Highly Digital Power Efficient Techniques for Serial Links

Rajesh Inti, 2011 .

A Low-Power Bidirectional Link With a Direct Data-Sequencing Blind Oversampling CDR

James E. Jaussi, Rajesh Inti, Sudip Shekhar, 2019, IEEE Journal of Solid-State Circuits.

26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS

Joseph Kennedy, Shreyas Sen, Tawfiq Musah, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

A 1.2–5Gb/s 1.4–2pJ/b serial link in 22nm CMOS with a direct data-sequencing blind oversampling CDR

James E. Jaussi, Bryan Casper, Sudip Shekhar, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration

Amr Elshazly, Pavan Kumar Hanumolu, Wenjing Yin, 2011, 2011 IEEE International Solid-State Circuits Conference.

A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS

James E. Jaussi, Bryan Casper, Sudip Shekhar, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

A 1.5GHz 1.35mW −112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity

Amr Elshazly, Pavan Kumar Hanumolu, Rajesh Inti, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS

Amr Elshazly, Pavan Kumar Hanumolu, Thomas Toifl, 2011, 2011 IEEE International Solid-State Circuits Conference.

A Scalable 32-to-56Gb/s 0.56-to-1.28pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28nm CMOS

James E. Jaussi, Bryan Casper, Rajesh Inti, 2021, 2021 IEEE Custom Integrated Circuits Conference (CICC).

Least Mean Square calibration method for VCO non-linearity

Un-Ku Moon, Rajesh Inti, Hariprasath Venkatram, 2010, 2010 International Conference on Microelectronics.

A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR

Amr Elshazly, Pavan Kumar Hanumolu, Brian Young, 2013, 2013 Symposium on VLSI Circuits.