Byung-Tae Choi

发表

Basis Matrix Representation of Morphological Filters with N-Dimensional Structuring Elements

Sung-Jea Ko, Aldo W. Morales, Kyung-Hoon Lee, 1997, J. Circuits Syst. Comput..

P‐95: Distortion of Sustain Waveform Relative to Displayed Area and Its Compensation for Stable Address Discharge in AC‐Plasma Display Panel

Heung-Sik Tae, Byung-Tae Choi, Kwang-Sik Lee, 2007 .

Optimal Variable Structure Controller with Higher Order Multilayer Neural Inverse Identifier

Cheol Hoon Park, Byung-Tae Choi, Soo-Young Lee, 1993 .

An effective de-interlacing technique using motion compensated interpolation

Sung-Jea Ko, You-Young Jung, Byung-Tae Choi, 2000, IEEE Trans. Consumer Electron..

P‐97: Analysis of Wall‐Voltage Variation During Address Period Using V(t) Closed Curves

Heung-Sik Tae, Byung-Tae Choi, Min Hur, 2007 .

Design of a New Self-Tuning PID Controller Using Neural Networks

Byung Kook Kim, Soo-Young Lee, Cheol Hoon Park, 1994 .

Analysis of luminance variation with display load and display pattern in AC-plasma display panels

Heung-Sik Tae, Byung-Tae Choi, Jae Kwang Lim, 2010, Displays.

New frame rate up-conversion using bi-directional motion estimation

Sung-Jea Ko, Sung-Hee Lee, Byung-Tae Choi, 2000, IEEE Trans. Consumer Electron..

A Novel De-interlacing Technique Using Bi-directional Motion Estimation

Sung-Jea Ko, Jae-Young Pyun, Byung-Tae Choi, 2003, ICCSA.

Robust noise reduction using a hierarchical motion compensation in noisy image sequences

Byung-Tae Choi, Eung-Tae Kim, Seung-Jong Choi, 2009, 2009 Digest of Technical Papers International Conference on Consumer Electronics.

Effects of Address-on-Time on Wall Voltage Variation during Address-Period in AC Plasma Display Panel

Heung-Sik Tae, Byung-Tae Choi, Hyung Dal Park, 2009, IEICE Trans. Electron..

P‐140: A Modified Selective Reset‐Waveform to Minimize Wall‐Voltage Variation During Address‐Period in Full‐HD PDP

Heung-Sik Tae, Byung-Tae Choi, Soo-ho Park, 2008 .