Chun-Hua Cheng

发表

Co-synthesis of data paths and clock control paths for minimum-period clock gating

Shih-Hsu Huang, Wen-Pin Tu, Chun-Hua Cheng, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Live demonstration: A low-power high-level synthesis system

Shih-Hsu Huang, Chun-Hua Cheng, Hua-Hsin Yeh, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Operation Scheduling for False Loop Free Circuits

Shih-Hsu Huang, Chun-Hua Cheng, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

Module binding for low power clock gating

Shih-Hsu Huang, Wen-Pin Tu, Chun-Hua Cheng, 2008, IEICE Electron. Express.

3D IC test scheduling with test pads considered

Shih-Hsu Huang, Chun-Hua Cheng, Ming-Hsuan Hsu, 2016, 2016 5th International Symposium on Next-Generation Electronics (ISNE).

Minimum-Period Register Binding

Shih-Hsu Huang, Chun-Hua Cheng, Shih-Hsu Huang, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

TSV number minimization using alternative paths

Shih-Hsu Huang, Chun-Hua Cheng, Chih-Hsien Kuo, 2011, 2011 IEEE International Conference on IC Design & Technology.

Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential

Shih-Hsu Huang, Chun-Hua Cheng, Wei-Ting Yen, 2007, EUC Workshops.

Operation scheduling for the synthesis of false loop free circuits

Shih-Hsu Huang, Chun-Hua Cheng, 2007, IEICE Electron. Express.

Accurate TSV Number Minimization in High-Level Synthesis

Shih-Hsu Huang, Chun-Hua Cheng, Chih-Hung Lee, 2011, J. Inf. Sci. Eng..

Surge current minimization in high-level synthesis

Shih-Hsu Huang, Chun-Hua Cheng, Jheng-Fu Yeh, 2009, 2009 IEEE International Symposium on Circuits and Systems.

An ILP Approach to the Slack Driven Scheduling Problem

Shih-Hsu Huang, Chun-Hua Cheng, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A formal approach to the slack driven scheduling problem in high-level synthesis

Shih-Hsu Huang, Chun-Hua Cheng, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Timing driven power gating in high-level synthesis

Shih-Hsu Huang, Chun-Hua Cheng, 2009, 2009 Asia and South Pacific Design Automation Conference.

Teaching three-dimensional system-in-package design automation in a semester course

Shih-Hsu Huang, Wen-Pin Tu, Chun-Hua Cheng, 2011, 2011 IEEE International Conference on Microelectronic Systems Education.

2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011, San Diego, CA, USA, June 5-6, 2011

Shih-Hsu Huang, Younghyun Kim, Wen-Pin Tu, 2011, MSE.

Synthesis of Anti-Aging Gated Clock Designs

Shih-Hsu Huang, Chun-Hua Cheng, Song-Bin Pan, 2009, J. Inf. Sci. Eng..

An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management

Shih-Hsu Huang, Chun-Hua Cheng, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, 2006 .

Watermark-strength-aware register binding

Shih-Hsu Huang, Chun-Hua Cheng, Tsung-Tang Lin, 2016, 2016 5th International Symposium on Next-Generation Electronics (ISNE).

Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization

Shih-Hsu Huang, Chun-Hua Cheng, 2010, J. Inf. Sci. Eng..

A post-processing approach to minimize TSV number for high-level synthesis of 3D ICs

Shih-Hsu Huang, Chun-Hua Cheng, Chih-Hung Lee, 2010, 2010 International Symposium on Computer, Communication, Control and Automation (3CA).

An ILP approach to surge current minimization in high-level synthesis

Shih-Hsu Huang, Chun-Hua Cheng, Jheng-Fu Yeh, 2009, IEICE Electron. Express.

Peak Power Minimization through Power Management Scheduling

Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

A formal approach to slack-driven high-level synthesis

Shih-Hsu Huang, Chun-Hua Cheng, Hua-Hsin Yeh, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Utilizing Power Management and Timing Slack for Low Power in High-Level Synthesis

Shih-Hsu Huang, Chun-Hua Cheng, Zong-Han Xie, 2018, 2018 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW).

Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization

Shih-Hsu Huang, Chun-Hua Cheng, Da-Chen Tzeng, 2009, J. Inf. Sci. Eng..

Clock Period Minimization with Minimum Delay Insertion

Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Power-mode-aware buffer synthesis for low-power clock skew minimization

Shih-Hsu Huang, Chun-Hua Cheng, 2016, IEICE Electron. Express.

An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management

Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, 2006, JCIS.

Three-dimension scheduling under multi-cycle interconnect communications

Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, 2005, IEICE Electron. Express.

Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits

Shih-Hsu Huang, Wen-Pin Tu, Chun-Hua Cheng, 2012, 17th Asia and South Pacific Design Automation Conference.

Power-Management Scheduling for Peak Power Minimization

Shih-Hsu Huang, Chun-Hua Cheng, 2008, J. Inf. Sci. Eng..

A Semester Course for Teaching Three-Dimensional System-in-Package Design Automation

Shih-Hsu Huang, Wen-Pin Tu, Chun-Hua Cheng, 2014 .

MINIMUM-POWER CLOCK GATING

Chia-Ming Chang, Shih-Hsu Huang, Chun-Hua Cheng, 2009 .

Layer assignment for maximizing the reliability of 3D ICs

Shih-Hsu Huang, Chun-Hua Cheng, Chun-Wei Lee, 2016, 2016 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

Test wrapper bandwidth assignment for minimizing the SoC test application time

Shih-Hsu Huang, Chun-Hua Cheng, Cheng-Hsun Nien, 2015, 2015 10th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

Grouping and placement of memory BIST controllers for test application time minimization

Shih-Hsu Huang, Chun-Hua Cheng, Chang-Han Yeh, 2016, 2016 5th International Symposium on Next-Generation Electronics (ISNE).

Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers

Shih-Hsu Huang, Chun-Hua Cheng, Wei-Kai Cheng, 2020, 2020 IEEE 38th VLSI Test Symposium (VTS).

Wafer bonding type selection for 3D IC designs

Shih-Hsu Huang, Chun-Hua Cheng, Hua-Hsin Yeh, 2013, 2013 8th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

Simultaneous wafer bonding type selection and layer assignment for TSV count minimization

Shih-Hsu Huang, Chun-Hua Cheng, Wei-Shuo Tzeng, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

Reliability-driven high-level synthesis with clock frequency considered

Shih-Hsu Huang, Chun-Hua Cheng, Wen-Zen Cheng, 2016, 2016 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).